Kwanghyun Cho

Reusable platform design methodology for SoC integration and verification

Today system-on-a-chip (SoC) is like a black hole which draws all the important IP/cores in a digital system. Current SoC design methodologies are no longer adequate to meet the challenges of SoC design productivity, design quality and diminishing time-to-market window. This paper describes an innovative SoC platform integration and verification design methodology to enhance design productivity based on IP reuse and IP-XACT standard. Platform integrator including RPTKit (reusable platform toolkit) is developed to improve the efficiency and reliability in platform integration, and platform verifier to improve verification setup time and work efficiency. Several cases of SoC platform designs substantiate the validity and capability of the platform integrator and verifier, which reduced the total SoC integration and verification time by more than 30%.

Multiagent supervisory control for antifault propagation in serial production systems

In this paper, a multiagent supervisory control methodology is proposed for antifault propagation in serial production systems by incorporating the idea of multiagent control within the fault-tolerant supervisory control scheme. Especially, the concept of antifault propagation between cascaded processes is established and the synthesis of agent supervisors is investigated based on this concept. A case study of a polypropylene polymerization process in the petrochemical industry is provided to illustrate the proposed control policy.

Design Automation of Pixel control block for productivity enhancement

To enhance design productivity, we propose a design methodology for automatic RTL generation of timing control block from user defined specification. We also provide error detector to reduce human error on specification to shorten design time. Experimental result shows that we can reduce overall design time by 70% while keeping area overhead lower than 5%, compared to that of manually optimized design.

Position Estimation Using Linear Hall Sensors for Permanent Magnet Linear Motor Systems

This paper proposes a new scaleless position estimation method. From the industrial perspective, the Hall sensor has several advantages: tiny size, light weight, extremely low cost, and insensitivity to environmental contamination and external disturbance. Compared to the square wave Hall sensor, the linear Hall sensor provides more detailed information along the position. However, for combining more than two linear Hall sensors, the sensor offset, the difference in scale, and the unwanted phase shift between them and the harmonics would decrease the validity and reliability of sensor measurement. The fast Fourier transform and the fixed point iteration method are applied to compensate for those issues without any low-pass filter or additional signal conditioning. The effectiveness of the proposed scheme is verified through a prototype permanent magnet linear synchronous motor system.

System-level simulation acceleration for architectural performance analysis using hybrid virtual platform system

Virtual platform is renowned for architecture exploration and validation, early software development, hardware/software co-development of Electronic System Level (ESL) System-on-Chip (SoC) design process. In Virtual Platform System (VPS), multi-level abstraction models should be properly adopted to achieve higher simulation performance while maintaining the platform design efforts as minimal as possible. For architecture validation, cycle-accurate system-level IP models are required to produce accurate performance simulation results. However, cycle-accurate model description often results in long modeling time and cycle inaccuracy due to complex timing behavior of given IPs. Therefore, RTL co-simulation has been widely used to avoid cycle-accurate model creation in system-level design process. In this paper, we suggest the Hybrid Virtual Platform System (H-VPS) to accelerate simulation speed by adopting co-emulation scheme into VPS while keeping cycle accuracy and minimizing risk of model creation. The experimental results of co-emulation show 12-48Kcps simulation speed, which is 6-62 times faster than VPS simulation time and is enough for architecture exploration and validation.

Varying mass estimation and force ripple compensation using Extended Kalman Filter for linear motor systems

In many industrial fields, the mass information of a moving system is important and necessary to prevent undesired motion or failure and to control the system in its desired trajectory. One simple solution could be direct measurement of the mass using a sensor such as force sensor and accelerometer. However, it requires additional cost increase. In addition, it is not easy to measure the mass of a moving part in many cases. For those reasons, in this research, an online varying mass estimation algorithm is designed using an Extended Kalman Filter (EKF) without any additional sensors. Furthermore, the lumped disturbance compensating algorithm, which was designed by the authors in the previous research using EKF, is combined to obtain further position tracking performance. The effectiveness of the suggested method is validated through simulations. Additional verification with experiments is planned for future work.

An efficient GPIO block design methodology using formalized SFR description

Recently, the size and complexity of a GPIO block, which implements IO paths for off-chip communications, have been increased significantly, so the possibility of making human errors in designing GPIO block has been increased. It is difficult to enhance GPIO design productivity because the architecture of Special Function Register (SFR) for GPIO block and multi-IO paths are fixed at relatively late stage of design activities in general. GPIO design also varies according to the designer, fabrication technology and product family, which makes design reuse difficult. This paper shows our analysis of the characteristics of SFRs in GPIO block, and a set-up of the methodology to formalize descriptions of specification to express various GPIO SFR architectures, and finally, design automation of the GPIO block. The experimental result shows that it is possible to describe various GPIO architectures with the proposed description methodology. In our case study, we succeeded on designing a GPIO block in a SOC platform which has more than 300 GPIO pins and 1,000 PAD pins. As a result, the amount of manual description for generating the GPIO block was reduced by 98%, compared to the traditional RTL description.