Kyu-Myung Choi

Gd-DTPA enhanced MR imaging in intracranial tuberculosis

SummaryTwenty-six patients with intracranial tuberculosis (Tb) (10 with acute meningitis, 5 with chronic meningitis, 5 with meningitic sequelae and 6 with localized tuberculoma(s) were examined with MR before and after Gd-DTPA enhancement (0.1 mmol/kg), using 2.0T superconducting unit, and the images were retrospectively analyzed and compared with CT scans. Without Gd-DTPA enhancement, the MR images were generally insensitive to detection of active meningeal inflammation and granulomas. The signal intensity of granulomas was usually isointense to gray matter on both T1- and T2-weighted images, whether they were associated with diffuse meningitis or presented as localized tuberculoma(s). A few granulomas showed focal hypointensity on T2-weighted images. Calcifications seen on CT of the meningitic sequelae group usually appeared markedly hypointense on all spin-echo sequences. On Gd-DTPA enhanced T1-weighted images, abnormal meningeal enhancement indicating active inflammation was conspicuous, and the granulomas often appeared as conglomerated ring-enhancing nodules, which seems to be characteristic of granulomas. Thin rim enhancement around the suprasellar calcifications were observed in two out of 5 patients with meningitic sequelae. Compared with CT, MR detected a few more ischemic infarcts, hemorrhagic infarcts, meningeal enhancement and granulomas in the acute meningitis group, but missed small calcifications in the basal cisterns well shown on CT in the sequelae group. Otherwise, MR generally matched CT scans. MR imaging appears to be superior to CT in evaluation of active intracranial Tb only if Gd-DTPA is used, while CT is better than MR in evaluating meningitic sequelae with calcification.

A 14 nm FinFET 128 Mb SRAM With V

Two 128 Mb dual-power-supply SRAM chips are fabricated in a 14 nm FinFET technology. A 0.064 μm2 and a 0.080 μm2 6T SRAM bitcells are designed for high-density (HD) and high-performance (HP) applications. To improve VMIN of the high-density SRAM, a negative bitline scheme (NBL) is adopted as a write-assist technique. Then, the disturbance-noise reduction (DNR) scheme is proposed as a read-assist circuit to improve the VMIN of the high-performance SRAM. The 128 Mb 6T-HD SRAM test-chip is fully demonstrated featuring 0.50 VMIN with 200 mV improvement by NBL, and 0.47 VMIN for the 128 Mb 6T-HP with 40 mV improvement by the DNR. Improved VMIN reduces 45.4% and 12.2% power-consumption of the SRAM macro with the help of each assist circuit, respectively.

_{\rm MIN}

In this work, we propose a SoC power estimation framework built on our system-level simulation environment. Our framework provides designers with the system-level power profile in a cycle-accurate manner. We target the framework to run fast and accurately, which is enabled by adopting different modeling techniques depending on the power characteristics of various IP blocks. The framework can be applied to any target SoC design

Enhancement Techniques for Low-Power Applications

The Multi-Threshold CMOS (MTCMOS) technology provides a solution to the high performance and low power design requirements of modern designs. While the low Vth transistors are used to implement the desired function, the high Vth transistors are used to cut off the leakage current. In this paper, we (i) examine the effectiveness of the MTCMOS technology for the Samsungs 0.18?m process, (ii) propose a new special flip-flop which keeps a valid data during the sleep mode, and (iii) develop a methodology which takes into account the new design issues related to the MTCMOS technology. Towards validating the proposed technique, a Personal Digital Assistant (PDA) processor has been implemented using the MTCMOS design methodology, and the 0.18?m process. The fabricated PDA processor operates at 333MHz, and consumes about 2?W of leakage power. Whereas the performance of the MTCMOS implementation is the same as that of the generic CMOS implementation, three orders of reduction in the leakage power has been achieved.

PowerV i P: Soc power estimation framework at transaction level

Power Gating has become one of the most widely used circuit design techniques for reducing leakage current. Its concept is very simple, but its application to standard-cell VLSI designs involves many careful considerations. The great complexity of designing a power-gated circuit originates from the side effects of inserting current switches, which have to be resolved by a combination of extra circuitry and customized tools and methodologies. In this tutorial we survey these design considerations and look at the best practice within industry and academia. Topics include output isolation and data retention, current switch design and sizing, and physical design issues such as power networks, increases in area and wirelength, and power grid analysis. Designers can benefit from this tutorial by obtaining a better understanding of implications of power gating during an early stage of VLSI designs. We also review the ways in which power gating has been improved. These include reducing the sizes of switches, cutting transition delays, applying power gating to smaller blocks of circuitry, and reducing the energy dissipated in mode transitions. Power Gating has also been combined with other circuit techniques, and these hybrids are also reviewed. Important open problems are identified as a stimulus to research.

An MTCMOS design methodology and its application to mobile computing

Meningioangiomatosis is a unique, rare hamartomatous lesion. Meningiomas arising in the background of meningioangiomatosis are rare conditions which pathologically and radiologically mimic invasive meningiomas, but have a benign clinical course in children and young adults. In this study, five such cases are reported. To our knowledge, this is the largest reported collection of meningiomas associated with meningioangiomatosis. Less immunoreactivity for progesterone receptor and high Ki‐67 labelling index are generally known to be associated with invasive meningiomas. However, high expression of progesterone receptor and low Ki‐67 labelling index in the present cases supports the idea that brain invasion is not an indicator of malignancy but an independent finding associated with meningiomas which have arisen from meningioangiomatosis. We emphasize the good prognosis of such tumours and discuss pathogenesis of meningiomas with meningioangiomatosis.

Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs

We present the method for five-step (pad-pad short-pad open-short-open) on-chip parasitic de-embedding. Its validation is verified by gate electrode resistance and input capacitance of transistors based on 45 -nm CMOS process. Optimized dummy structures to remove the parasitic components due to the pad and routing metal are proposed. Parameters extracted by the proposed method have excellent physical and theoretical trends.

Childhood meningiomas associated with meningioangiomatosis: report of five cases and literature review

For successful SoC design, efficient and scalable communication architecture is crucial. Some bus interconnects now provide configurable structures to meet this requirement of an SoC design. Furthermore, bus IP vendors provide software tools that automatically generate RTL codes of a bus once its designer configures it. Configurability, however, imposes more challenges upon designers because complexity involved in optimization increases exponentially as the number of parameters grows. In this paper, we present a novel approach with which effort requirement can be dramatically reduced. An automated optimization tool we developed is used and it exploits a genetic algorithm for fast design exploration. This paper shows that the time for the optimizing task can be reduced by more than 90% when the tool is used and, more significantly the task can be done without an experts hand while ending up with a better solution.

Five-Step (Pad–Pad Short–Pad Open–Short–Open) De-Embedding Method and Its Verification

Abstract We have studied the relationship between the morphology and the electro-optic properties of liquid crystal-polymer composite (LCPC) materials. The materials consist of the liquid crystal (80° by weight) and the polymerizable mixture (20° by weight) composed of the monofunctional monomer, the oligomer, and the multifunctional acryl monomer. The results show that the electro-optic properties such as the driving voltage and the transmittance depend strongly on the polymer species used. When the solubility between the liquid crystal and the growing polymers formed during the polymerization process is low and the speed of phase separation is fast, the morphology shows a ‚Network’ type, the liquid crystal exhibits a continuous phase through the sample, and such a film scatters light strongly in the off state. The maximum transmittance in the on state depends primarily on the polymer morphology and secondly on the solubility between the polymers and the liquid crystal in the ‚Network’ type LCPC film. Th...

Fast exploration of parameterized bus architecture for communication-centric SoC design

3D stacked memory enables more off-chip DDR memories. Redesigning existing IPs to exploit the increased memory parallelism will be prohibitively costly. In our work, we propose a practical approach to exploit the increased bandwidth and reduced latency of multiple off-chip DDR memories while reusing existing IPs without modification. The proposed approach is based on two new concepts: transaction id renaming and distributed soft arbitration. We present two on-chip network components, request parallelizer and read data serializer, to realize the concepts. Experiments with synthetic test cases and an industrial strength DTV SoC design show that the proposed approach gives significant improvements in total execution cycle (21.6%) and average memory access latency (31.6%) in the DTV case with a small area overhead (30.1% in the on-chip network, and less than 1.4% in the entire chip).