Byoung-Gon Yu

A Low Power Phase-Change Random Access Memory using a Data-Comparison Write Scheme

A low power PRAM using a data-comparison write (DCW) scheme is proposed. The PRAM consumes large write power because large write currents are required during long time. At first, the DCW scheme reads a stored data during write operation. And then, it writes an input data only when the input and stored data are different. Therefore, it can reduce the write power consumption to a half. The 1K-bit PRAM test chip with 128times8bits is implemented with a 0.8mum CMOS technology with a 0.5mum GST cell.

Dielectric and ferroelectric response as a function of annealing temperature and film thickness of sol-gel deposited Pb(Zr0.52Ti0.48)O3 thin film

We report the thickness and annealing temperature dependence of the structural, morphological, compositional, and electrical properties including ferroelectric characteristics of Pb(Zr0.52Ti0.48)O3 thin films deposited by a sol-gel method. The thickness and annealing temperature of the films were in the range of 0.12–0.36 μm and 520–670 °C, respectively. The crystalline structure and growth behavior of the films have been studied by x-ray diffraction, scanning electron microscopy, and atomic force microscopy. It is demonstrated that the weak ac electric field dependence of the permittivity of the films in terms of the Rayleigh law can be explained. The coercive field obtained from a sweep up and down schedule of the capacitance-voltage curves is asymmetrical and shows different behavior according to the annealing temperature and thickness. We also show that the activation energy coefficient, γ, obtained from frequency dependent polarization-electric field hysteresis loops is related to the annealing tempe...

Sb-Se-based phase-change memory device with lower power and higher speed operations

A phase-change material of Sb/sub 65/Se/sub 35/ was newly proposed for the nonvolatile memory applications. The fabricated phase-change memory device using Sb/sub 65/Se/sub 35/ showed a good electrical threshold switching characteristic in the dc current-voltage (I-V) measurement. The programming time for set operation of the memory device decreased from 1 /spl mu/s to 250 ns when Sb/sub 65/Se/sub 35/ was introduced in place of the conventionally employed Ge/sub 2/Sb/sub 2/Te/sub 5/ (GST). The reset current of Sb/sub 65/Se/sub 35/ device also dramatically reduced from 15 mA to 1.6 mA, compared with that of GST device. These results are attributed to the low melting temperature and high crystallization speed of Sb/sub 65/Se/sub 35/ and will contribute to lower power and higher speed operations of a phase-change nonvolatile memory.

Fabrication and characterization of MFISFET using Al2O3 insulating layer for non-volatile memory

Abstract Metal-ferroelectric-insulator-semiconductor (MFIS) structures including an Al2O3 insulator layer and a SBT ferroelectric film are fabricated with their optimum thicknesses extracted by computer simulation, and then electrical properties of MFIS structures are investigated. In Pt/Al2O3/Si structure, no hysteresis and low leakage current of 7.5 × 10−9A/cm2 have been observed. The MFIS structure, Pt/SBT/Al2O3/Si, shows a memory window width of 1.2 V at an operation voltage of 5 V and a gate leakage current density of 7 × 10−8A/cm2at 1 V. Fatigue characteristics of the MFIS structure are also studied.

Crystallization Behavior and Physical Properties of Sb-Excess Ge2Sb2 + x Te5 Thin Films for Phase Change Memory (PCM) Devices

The crystallization behavior of antimony(Sb)-excess Ge 2 Sb 2+x Te 5 was examined. Sb-excess GST showed crystallization (T c ) and melting (T M ) temperatures of 205 and 550°C, respectively, slightly higher T C and lower T M values than stoichiometric Ge 2 Sb 2 Te 5 compounds. It also showed a substantially different crystallization behavior compared to the stoichiometric Ge 2 Sb 2 Te 5 composition. The resulting Sb-excess GeSbTe thin film showed a grain growth dominated crystallization behavior.

SrTa2O6 Thin Films Deposited by Plasma-Enhanced Atomic Layer Deposition

SrTa2O6 (STO) thin films were prepared by plasma-enhanced atomic layer deposition (PEALD) with an alternating supply of reactant sources, Sr[Ta(C2H5O)5(C4H10NO)]2 {strontium bis-[tantalum penta-ethoxide dimethyllaminoethoxide]; Sr(Ta(OEt)5dmae)2} and O2 plasma. It was observed that the uniform and conformal STO thin films were successfully deposited using PEALD and the film thickness per cycle was saturated at approximately 0.8 A at 300°C. Electrical properties of STO thin films prepared on Pt/SiO2/Si substrates at various annealing temperatures were investigated. While the grain size and dielectric constant of STO films increased with increasing annealing temperature, the leakage current characteristics of STO films slightly deteriorated. The leakage current density of a 40 nm STO film annealed at 600°C was approximately 5×10-8 A/cm2 at 3 V.

Polycrystalline silicon-germanium heating layer for phase-change memory applications

This letter reports on the performance improvement of phase-change memory (PCM) cells by applying silicon-germanium (SiGe) alloys as resistive heating layers. The in situ doped polycrystalline Si0.75Ge0.25 films, lying under holes filled with a Ge2Sb2Te5 (GST) phase-change material in a pore-style configuration, promoted the temperature rise and phase transition in the GST. The SiGe heating layer caused drastic reduction in both set and reset currents compared to a conventional TiN heater material. The threshold voltages of the PCM cells were almost uniform irrespective of the kind of heating layers. It is considered that this beneficial effect of the SiGe heating layer originates from the high electrical resistivity and low thermal conductivity of a SiGe alloy.

Nonvolatile memory thin-film transistors using an organic ferroelectric gate insulator and an oxide semiconducting channel

Organic–inorganic hybrid-type nonvolatile memory thin-film transistors using an organic ferroelectric gate insulator and an oxide semiconducting active channel are a very promising solution to the memory devices having both features of low-cost and high-performance, which are embeddable into the next-generation flexible and transparent electronics. In this paper, we discuss some important issues for this proposed device, such as device structure design, process optimization and memory array integration. Promising feasible applications and remaining technology issues to solve were also discussed.

Characterization of silver-saturated Ge–Te chalcogenide thin films for nonvolatile random access memory

Programmable metallization cell structure with a device diameter of 2μm composed of Ag–Ge–Te chalcogenide films was prepared by a cosputtering technique at room temperature. The device with a 150nm thick Ag30(Ge0.3Te0.7)70 electrolyte switches at 0.2V from an “off” state resistance Roff close to 106Ω to an “on” resistance state Ron more than four orders of magnitude lower for this programming current. The switching characteristics were closely related with a diffusion of silver anode into silver-saturated GeTe electrolyte films.

Effect of ZnO channel thickness on the device behaviour of nonvolatile memory thin film transistors with double-layered gate insulators of Al2O3 and ferroelectric polymer

Poly(vinylidene fluoride trifluoroethylene) and ZnO were employed for nonvolatile memory thin film transistors as ferroelectric gate insulator and oxide semiconducting channel layers, respectively. It was proposed that the thickness of the ZnO layer be carefully controlled for realizing the lower programming voltage, because the serially connected capacitor by the formation of a fully depleted ZnO channel had a critical effect on the off programming voltage. The fabricated memory transistor with Al/P(VDF–TrFE) (80 nm)/Al2O3 (4 nm)/ZnO (5 nm) exhibits encouraging behaviour such as a memory window of 3.8 V at the gate voltage of −10 to 12 V, and 107 on/off ratio, and a gate leakage current of 10−11 A.