Young-Sam Park

Sb-Se-based phase-change memory device with lower power and higher speed operations

A phase-change material of Sb/sub 65/Se/sub 35/ was newly proposed for the nonvolatile memory applications. The fabricated phase-change memory device using Sb/sub 65/Se/sub 35/ showed a good electrical threshold switching characteristic in the dc current-voltage (I-V) measurement. The programming time for set operation of the memory device decreased from 1 /spl mu/s to 250 ns when Sb/sub 65/Se/sub 35/ was introduced in place of the conventionally employed Ge/sub 2/Sb/sub 2/Te/sub 5/ (GST). The reset current of Sb/sub 65/Se/sub 35/ device also dramatically reduced from 15 mA to 1.6 mA, compared with that of GST device. These results are attributed to the low melting temperature and high crystallization speed of Sb/sub 65/Se/sub 35/ and will contribute to lower power and higher speed operations of a phase-change nonvolatile memory.

Crystallization Behavior and Physical Properties of Sb-Excess Ge2Sb2 + x Te5 Thin Films for Phase Change Memory (PCM) Devices

The crystallization behavior of antimony(Sb)-excess Ge 2 Sb 2+x Te 5 was examined. Sb-excess GST showed crystallization (T c ) and melting (T M ) temperatures of 205 and 550°C, respectively, slightly higher T C and lower T M values than stoichiometric Ge 2 Sb 2 Te 5 compounds. It also showed a substantially different crystallization behavior compared to the stoichiometric Ge 2 Sb 2 Te 5 composition. The resulting Sb-excess GeSbTe thin film showed a grain growth dominated crystallization behavior.

Polycrystalline silicon-germanium heating layer for phase-change memory applications

This letter reports on the performance improvement of phase-change memory (PCM) cells by applying silicon-germanium (SiGe) alloys as resistive heating layers. The in situ doped polycrystalline Si0.75Ge0.25 films, lying under holes filled with a Ge2Sb2Te5 (GST) phase-change material in a pore-style configuration, promoted the temperature rise and phase transition in the GST. The SiGe heating layer caused drastic reduction in both set and reset currents compared to a conventional TiN heater material. The threshold voltages of the PCM cells were almost uniform irrespective of the kind of heating layers. It is considered that this beneficial effect of the SiGe heating layer originates from the high electrical resistivity and low thermal conductivity of a SiGe alloy.

Etching Characteristics of Ge2Sb2Te5 Using High-Density Helicon Plasma for the Nonvolatile Phase-Change Memory Applications

We investigated the etching behaviors of GST, which has been mainly employed for the realization of phase-change type nonvolatile memory devices, using high-density helicon plasma etching system under the various etching gas conditions. Our results provide the etch rates of GST thin films as a function of gas mixing ratio when the gas mixtures of Ar/Cl2 and Ar/CHF3 were applied. It was found that the etch selectivities of GST to SiO2 and to TiN were optimized at Ar/Cl2 = 90/10 and Ar/CHF3 = 80/20, respectively. It was also confirmed that there is no significant change in composition of GST after the etching process. Using the obtained results, we can design the etching process in a systematic way for the fabrication of GST-loaded phase-change type memory devices.

Phase-Change-Driven Programmable Switch for Nonvolatile Logic Applications

A new device concept for a programmable switch employing a phase-change memory element was proposed, in which a unique four-terminal structure having two operating channels was so designed as to effectively separate two functions of programming and pass-gating. The proposed device was successfully fabricated, and its operational behaviors were demonstrated.

Nanoscale Observations on the Degradation Phenomena of Phase-Change Nonvolatile Memory Devices Using Ge2Sb2Te5

For the realization of highly reliable phase-change memory devices, it is very important to understand their operational failure modes. We presented the failure behavior of devices using Ge2Sb2Te5 (GST) as a phase-change material, in which the drift phenomenon of the current condition for reset and the degradation of switching speed for set were typically observed for some fabricated devices. The studies by a transmission electron microscopy (TEM) and an energy-dispersive X-ray spectroscopy (EDS) suggested that the compositional change of GST within the device is the reason for these results. It was also confirmed that the unexpected formation of a Ge–Te-based alloy may make the set speed slow down to 100 µs.

Dry Etching of Ge2Sb2Te5 Thin Films into Nanosized Patterns Using TiN Hard Mask

We investigated dry etching methods for the patterning of nanosized Ge2Sb2Te5 (GST) patterns using high-density helicon plasma etching system. It was found that GST patterns of 10-nm-order size could not be formed in a suitable way owing to the damage of undesirable under-cut when the etching process was performed in gas mixtures of Ar/Cl2 using a SiO2 hard mask. In this work, a hard mask of TiN was therefore chosen for employing a CF4-based gas mixture for GST etching, in which the gas mixing ratios of Ar/Cl2 and Ar/CF4 were carefully controlled for TiN and GST patterning processes, respectively. Using these optimized patterning conditions, tens-of-nanometer-sized GST line and square-dot patterns could be successfully obtained with good profiles and uniformity.

Low power and high speed phase-change memory devices with silicon-germanium heating layers

The switching speed and the reliability of the phase-change memory (PCM) device employing a SiGe film as a heating layer were compared with those of the control device employing a conventional TiN heating layer. The influence of the semiconducting nature of the SiGe film on PCM operation was investigated. The critical pulse width for the onset of a set process was reduced to less than about 50% by substitution of SiGe for TiN. The cycling endurance value for the PCM device with a SiGe heating layer was comparable to that of the control device, which indicated that the introduction of a SiGe film did not induce reliability degradation. The heterojunction between the GeSbTe and SiGe layers was so leaky that the effect of the semiconduction type of SiGe was negligible. The reset current was saturated at a minimum value with increasing resistivity of a SiGe film, which was attributed to the resistance lowering of SiGe at high temperature. The PCM device with a SiGe heating layer was successively fabricated us...

Electrical Characterization of Nonvolatile Phase-Change Memory Devices Using Sb-Rich Ge–Sb–Te Alloy Films

We modified the composition of Ge–Sb–Te alloys for phase-change-type nonvolatile memory devices to realize more reliable memory operations. It is expected that the stability of the low-resistance crystalline phase of the Ge–Sb–Te alloy can be improved when an appropriate amount of excess Sb is added to conventional stoichiometric Ge2Sb2Te5 (GST), because a phase transition directly occurs from the amorphous phase to the more conductive hcp phase without the formation of the less conductive metastable fcc phase. Phase-change memory devices using Sb-rich Ge–Sb–Te alloys were fabricated, where the Sb atomic ratio was controlled to be from 31 to 47%. The effect of Sb addition to GST on the phase-change switching characteristics was investigated in terms of the electrical behaviors of the fabricated memory devices. For the set operations, the threshold voltage (Vth) for electronic switching and the required current for set were observed to decrease with increasing Sb composition. The data endurance of memory devices under repetitive operations was measured to be in the range from 1×105 to 2×106 cycles. From the investigations using energy dispersive X-ray spectroscopy (EDS), it was clearly shown that there was no phase separation and/or marked compositional change of the device experiencing 2×106 successive operations, when the Sb atomic ratio in the Ge–Sb–Te alloy was 39%.

The Characteristics of Seebeck Coefficient in Silicon Nanowires Manufactured by CMOS Compatible Process

Silicon nanowires are patterned down to 30 nm using complementary metal-oxide-semiconductor (CMOS) compatible process. The electrical conductivities of n-/p-leg nanowires are extracted with the variation of width. Using this structure, Seebeck coefficients are measured. The obtained maximum Seebeck coefficient values are 122 μV/K for p-leg and −94 μV/K for n-leg. The maximum attainable power factor is 0.74 mW/m K2 at room temperature.