Byoung W. Min

A 45 nm gate length high performance SOI transistor for 100 nm CMOS technology applications

In this report, a high performance silicon-on-insulator (SOI) transistor for the 100 nm CMOS technology node is presented. Partially depleted (PD) transistors were fabricated in a 1000 /spl Aring/-thick silicon film with gate lengths down to 45 nm, using a 16 /spl Aring/ nitrided gate oxide. At an operating voltage of 1.2 V, self-heated drive currents of 940 /spl mu/A//spl mu/m and 460 /spl mu/A//spl mu/m were achieved at 20 nA//spl mu/m for NMOS and PMOS respectively. Floating body effects (FBE) were minimized by special diode junction engineering to achieve maximum overall performance. A measured median stage delay of 6 ps was achieved on an inverter-fan-out-1 ring oscillator at 1.3 V at a total N+P leakage of 30 nA//spl mu/m. The exceptional AC performance of this technology is among the highest reported in the literature at this low transistor leakage and operating voltage.

Partial trench isolated body-tied (PTIBT) structure for SOI applications

Silicon on insulator (SOI) technology has gained interest to provide improvements in speed and power consumption over bulk technologies. However, floating body effects of SOI devices such as kinks, parasitic bipolar action and hysteretic propagation delay have retarded its application. To eliminate these undesirable effects several body-tied structures have been suggested, but all generally suffer from adverse costs such as performance degradation and/or process complexity. We propose a novel body-tied structure, adding simple partial trench isolation, which effectively suppresses the floating body effects without performance degradation.

Hot carrier enhanced gate current and its impact on short channel nMOSFET reliability with ultra-thin gate oxides

We have investigated hot carrier stress degradation for short channel (100 nm and 80 nm) nMOSFETs with ultra-thin gate oxides (2.5 nm). Under high drain bias, gate current was measured well above that is expected from direct tunneling itself We have found that this hot carrier enhanced gate current mechanism plays a significant role in the degradation of nMOSFETs. The degradation under very accelerated stress bias, where hot carrier enhanced gate current is dominant, was relatively insensitive to stress bias and time, compared to the degradation under low voltage hot carrier stress. Unless properly considered, the additional mechanism can cause the extrapolated lifetime to be overestimated.

High performance partially depleted SOI using spike RTA

Thinner Si body (700 /spl Aring/) SOI CMOS was successfully demonstrated with spike RTA on 0.13 /spl mu/m technology with 45 nm gate lengths and 16/spl Aring/ gate oxide. Spike RTA exhibited excellent short channel effect and lower miller capacitance (Cmiller), resulting in faster circuit speed and lower dynamic power compared to the conventional RTA. Spike RTA also showed comparable floating body effects and stress induced current degradation.

Effects of SOI film thickness on high-performance microprocessor by 0.13 /spl mu/m Partially-Depleted SOI CMOS technology

This paper describes how SOI film thickness affects performance and power consumption of a Partially-Depleted (PD) SOI microprocessor. System level speed/power performance will be compared directly between chips fabricated with different SOI film thickness. The performance improvement is also supported by device level and macro circuit level comparison. Yield issues associated with thinner SOI will also be addressed.

Vdd impact on propagation pulse width variation in PD SOI circuits

Pulse width variation through open-ended chains in partially depleted SOI is investigated. Vdd impact on the pulse variation (either compression or stretching) is intensively studied, as well as temperature and illumination contributions. A physical model using well-known capacitive coupling, generation, and recombination concepts is proposed with experimental data.