Byoungkeun Son

Highly cost effective and high performance 65nm S/sup 3/ (stacked single-crystal Si) SRAM technology with 25F/sup 2/, 0.16um/sup 2/ cell and doubly stacked SSTFT cell transistors for ultra high density and high speed applications

In order to meet the great demands for higher density SRAM in all area of SRAM applications, the 25F/sup 2/S/sup 3/ (stacked single-crystal Si ) SRAM cell, which is a truly 3-dimensional device by stacking the load PMOS and the pass NMOS Tr. on the planar pull-down Tr., respectively in different levels, was developed and was reported in our previous study for low power applications. The previous reported S3 technology could not provide the high performance because it was developed for low power applications without salicide and high performance transistors. For the high performance transistor, the low thermal and low resistance processes are essential. In this study, the high performance CMOS transistors with 65nm gate length and l.6nm gate oxide, low resistance CVD Co for the small contact holes, and selectively formed CoSix in the peripheral area are added to the smallest 25F/sup 2/ double stacked S/sup 3/ SRAM cell for ultra high speed applications with the highest density such as 288M bits.

Prognostic values of KAI1 and survivin expression in an infiltrating ductal carcinoma of the breast

Aims: To investigate KAI1 and survivin expression in infiltrating ductal carcinomas, and to evaluate the relationship between clinicopathological factors and KAI1 and survivin expression levels in breast cancers. Methods and Results: KAI and survivin expression levels were measured in 62 patients, using immunohistochemical staining. Western blot analysis was performed on eight frozen cases. DNA ploidy was determined by flow cytometry. The results of the KAI1 expression analyses were as follows: in 14 cases (22.6%) levels were preserved (++), in 30 cases (48.4%) levels were reduced (+), in 18 cases (29.0%) no KAI1 expression was detected, so these were designated “lost’ (−). Results of assessments of survivin expression were as follows: six cases (9.7%) were strong positive (++), 28 cases (45.15%) were positive (+), and 28 cases (45.15%) were negative. Survivin (p=50.0009) and KAI1 (p=50.0091) expression levels were directly correlated with survival rate. However, no significant difference was determined to exist between survivin and KAI1 expression levels and the clinicopathological factors. DNA ploidy did not correlate with survivin and KAI1 expression levels and survival rate. Four different groups, according to their survivin and KAI1 expression levels, correlated with the clinical stage and survival rate. Conclusion: KAI1 and survivin expression levels might be prognostic factors in breast cancers.

Highly reliable vertical NAND technology with biconcave shaped storage layer and leakage controllable offset structure

The performance and reliability of 3-D NAND cells fabricated by TCAT (Terabit Cell Array Transistor) technology have been improved significantly via a damascened metal gates and a controlled offset between BL contact and select transistor. The damascened metal gate providing sufficiently low resistance is achieved by adopting a novel metal process. Highly suppressed disturbance property is achieved by the appropriate offset which reduces the leakage current through the select transistor. It is proved that the TCAT NAND is a manufacturable technology in terms of reliability as well as performance in a channel hole with a diameter of 90nm.

High Speed and Highly Cost effective 72M bit density S 3 SRAM Technology with Doubly Stacked Si Layers, Peripheral only CoSix layers and Tungsten Shunt W/L Scheme for Standalone and Embedded Memory

Highly cost effective and high speed 72M bit density S3 SRAM technology was successfully achieved for standalone memory and embedded memory with selective epitaxial growth of Si films, low thermal SSTFT process , periphery only Co salicidation, and W shunt wordline scheme.

Soft error immune 0.46 /spl mu/m/sup 2/ SRAM cell with MIM node capacitor by 65 nm CMOS technology for ultra high speed SRAM

The smallest SRAM cell, 0.46 um/sup 2/, is realized by a single pitch cell layout, gate poly trim mask technique, 80 nm contact holes formed by polymer attaching process, and a 193 nm ArF lithography process. The MIM (metal-insulator-metal) node capacitor is developed and used for the first time in the SRAM cell to reduce the radiation induced soft error rate, dramatically. The high performance transistors are developed with a channel length of 70 nm, plasma nitrided 13 /spl Aring/ gate oxide, low thermal budget sidewall spacer, and CoSix.

Channel Coupling phenomenon as scaling barrier of NAND flash memory beyond 20nm node

A new program disturbance phenomenon appeared from sub 40nm-node NAND flash cell is presented firstly which is named as BTBT Leakage Burst by Channel Coupling (abbr. “Channel Coupling”). With scaling down, the neighboring program channel of 0V grabs strongly the boosted channel at program-inhibited active line not to rise up at the active sidewall and simultaneously, its potential at Si surface is tried to be raised by help of pass voltage. The competition induces the sharp band-bending and thereby sudden enhancement of BTBT leakage, resulting in suppressing channel boosting. In order to overcome “Channel Coupling” appeared at 1X-nm node as a scaling barrier, the air gap in shallow trench isolation is suggested and the effect of the air gap is verified by simulation.

65nm high performance SRAM technology with 25F2 0.16/spl mu/m/sup 2/ S/sup 3/ (stacked single-crystal Si) SRAM cell, and stacked peripheral SSTFT for ultra high density and high speed applications

For the first time, the 65nm high performance transistor technology and the highly compacted double stacked S/sup 3/ SRAM cell with a size of 25F/sup 2/, and 0.16/spl mu/m/sup 2/ has been combined for providing the high density and high density solutions which can make the breakthrough in the field of the cache memory products and the network memory products. The SSTFT (single-crystal silicon thin film transistor) is used not only for cell transistors but also for peripheral transistors. The selective Co silicidation techniques is developed for low resistance. By utilizing this technology, the high performance 288Mb synchronous SRAM product will be fabricated.