Han-Byung Park

Highly cost effective and high performance 65nm S/sup 3/ (stacked single-crystal Si) SRAM technology with 25F/sup 2/, 0.16um/sup 2/ cell and doubly stacked SSTFT cell transistors for ultra high density and high speed applications

In order to meet the great demands for higher density SRAM in all area of SRAM applications, the 25F/sup 2/S/sup 3/ (stacked single-crystal Si ) SRAM cell, which is a truly 3-dimensional device by stacking the load PMOS and the pass NMOS Tr. on the planar pull-down Tr., respectively in different levels, was developed and was reported in our previous study for low power applications. The previous reported S3 technology could not provide the high performance because it was developed for low power applications without salicide and high performance transistors. For the high performance transistor, the low thermal and low resistance processes are essential. In this study, the high performance CMOS transistors with 65nm gate length and l.6nm gate oxide, low resistance CVD Co for the small contact holes, and selectively formed CoSix in the peripheral area are added to the smallest 25F/sup 2/ double stacked S/sup 3/ SRAM cell for ultra high speed applications with the highest density such as 288M bits.

Extended scalability of perpendicular STT-MRAM towards sub-20nm MTJ node

In this article, we report the first experimental demonstration of sub-20nm MTJ cells for investigating the downscaling feasibility of spin-transfer torque (STT) MRAM, one of the most promising candidates to replace conventional memories. We demonstrate the STT switching of 17nm node P-MTJ cells, the smallest feature size ever reported, utilizing perpendicular materials possessing high interface anisotropy of 2.5 erg/cm2 and improved integration processes to achieve reproducible switching with critical current (Ic) of 44uA, tunneling magneto-resistance (TMR) ratio of 70% and thermal stability factor (E/kBT) of 34.

High Speed and Highly Cost effective 72M bit density S 3 SRAM Technology with Doubly Stacked Si Layers, Peripheral only CoSix layers and Tungsten Shunt W/L Scheme for Standalone and Embedded Memory

Highly cost effective and high speed 72M bit density S3 SRAM technology was successfully achieved for standalone memory and embedded memory with selective epitaxial growth of Si films, low thermal SSTFT process , periphery only Co salicidation, and W shunt wordline scheme.

Soft error immune 0.46 /spl mu/m/sup 2/ SRAM cell with MIM node capacitor by 65 nm CMOS technology for ultra high speed SRAM

The smallest SRAM cell, 0.46 um/sup 2/, is realized by a single pitch cell layout, gate poly trim mask technique, 80 nm contact holes formed by polymer attaching process, and a 193 nm ArF lithography process. The MIM (metal-insulator-metal) node capacitor is developed and used for the first time in the SRAM cell to reduce the radiation induced soft error rate, dramatically. The high performance transistors are developed with a channel length of 70 nm, plasma nitrided 13 /spl Aring/ gate oxide, low thermal budget sidewall spacer, and CoSix.

65nm high performance SRAM technology with 25F2 0.16/spl mu/m/sup 2/ S/sup 3/ (stacked single-crystal Si) SRAM cell, and stacked peripheral SSTFT for ultra high density and high speed applications

For the first time, the 65nm high performance transistor technology and the highly compacted double stacked S/sup 3/ SRAM cell with a size of 25F/sup 2/, and 0.16/spl mu/m/sup 2/ has been combined for providing the high density and high density solutions which can make the breakthrough in the field of the cache memory products and the network memory products. The SSTFT (single-crystal silicon thin film transistor) is used not only for cell transistors but also for peripheral transistors. The selective Co silicidation techniques is developed for low resistance. By utilizing this technology, the high performance 288Mb synchronous SRAM product will be fabricated.