Hoosung Cho

Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node

For the first time, the 3 dimensionally stacked NAND Flash memory, is developed by implementing S3 (single-crystal Si layer stacking) technology, which was used to develop S3 SRAM previously. The NAND cell arrays are formed on the ILD as well as on the bulk to double the memory density without increasing the chip size. The feasibility of the technology was proven by the successful operation of 32 bit NAND flash memory cell strings with 63nm dimension and TANOS structures. The novel NAND cell operational scheme, so called SBT (source-body tied) scheme, is presented to maximize the advantages of 3 dimensionally stacked NAND cell structures

Highly cost effective and high performance 65nm S/sup 3/ (stacked single-crystal Si) SRAM technology with 25F/sup 2/, 0.16um/sup 2/ cell and doubly stacked SSTFT cell transistors for ultra high density and high speed applications

In order to meet the great demands for higher density SRAM in all area of SRAM applications, the 25F/sup 2/S/sup 3/ (stacked single-crystal Si ) SRAM cell, which is a truly 3-dimensional device by stacking the load PMOS and the pass NMOS Tr. on the planar pull-down Tr., respectively in different levels, was developed and was reported in our previous study for low power applications. The previous reported S3 technology could not provide the high performance because it was developed for low power applications without salicide and high performance transistors. For the high performance transistor, the low thermal and low resistance processes are essential. In this study, the high performance CMOS transistors with 65nm gate length and l.6nm gate oxide, low resistance CVD Co for the small contact holes, and selectively formed CoSix in the peripheral area are added to the smallest 25F/sup 2/ double stacked S/sup 3/ SRAM cell for ultra high speed applications with the highest density such as 288M bits.

A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure

Recently, 3-dimensional (3D) memories have regained attention as a potential future memory solution featuring low cost, high density and high performance. We present a 3D double stacked 4Gb MLC NAND flash memory device with shared bitline structure, with a cell size of 0.0021mum2/bit per unit feature area. The device is designed to support 3D stacking and fabricated by S3 and 45nm floating-gate CMOS technologies.

Static noise margin of the full DG-CMOS SRAM cell using bulk FinFETs (Omega MOSFETs)

The operational six-transistor SRAM cell was experimentally demonstrated using bulk FinFET CMOS technology. A cell size of 0.79 /spl mu/m/sup 2/ was achieved by 90 nm node technology, with stable operation at 1.2 V using 4 levels of W and Al interconnects. Static noise margin of 280 mV was obtained at V/sub cc/ of 1.2 V. To our knowledge, this represents the first experimental demonstration of a fully integrated bulk FinFET SRAM cell.

Highly area efficient and cost effective double stacked S/sup 3/ (stacked single-crystal Si) peripheral CMOS SSTFT and SRAM cell technology for 512M bit density SRAM

For the first time, the highest density SRAM, such as 512M bit SRAM, is developed by implementing the smallest 25F/sup 2/S/sup 3/ SRAM cell technology, whose cell size is 0.16/spl mu/m/sup 2/, and area saving peripheral SSTFT (stacked single-crystal thin film transistor) technology. The SSTFT are used as the peripheral CMOS transistors as well as the cell transistors to save area to make the SRAM products comparative to the DRAM cell based products in the density and the cost. In the S/sup 3/ SRAM cell, the load PMOS and pass NMOS transistors are stacked over the planar pull-down NMOS transistors to drastically reduce the cell size. Also, in a periphery, the core logic transistors are stacked on the ILD to save the layout area for maximizing cell efficiency for the products.

Highly reliable vertical NAND technology with biconcave shaped storage layer and leakage controllable offset structure

The performance and reliability of 3-D NAND cells fabricated by TCAT (Terabit Cell Array Transistor) technology have been improved significantly via a damascened metal gates and a controlled offset between BL contact and select transistor. The damascened metal gate providing sufficiently low resistance is achieved by adopting a novel metal process. Highly suppressed disturbance property is achieved by the appropriate offset which reduces the leakage current through the select transistor. It is proved that the TCAT NAND is a manufacturable technology in terms of reliability as well as performance in a channel hole with a diameter of 90nm.

Soft error immune 0.46 /spl mu/m/sup 2/ SRAM cell with MIM node capacitor by 65 nm CMOS technology for ultra high speed SRAM

The smallest SRAM cell, 0.46 um/sup 2/, is realized by a single pitch cell layout, gate poly trim mask technique, 80 nm contact holes formed by polymer attaching process, and a 193 nm ArF lithography process. The MIM (metal-insulator-metal) node capacitor is developed and used for the first time in the SRAM cell to reduce the radiation induced soft error rate, dramatically. The high performance transistors are developed with a channel length of 70 nm, plasma nitrided 13 /spl Aring/ gate oxide, low thermal budget sidewall spacer, and CoSix.

65nm high performance SRAM technology with 25F2 0.16/spl mu/m/sup 2/ S/sup 3/ (stacked single-crystal Si) SRAM cell, and stacked peripheral SSTFT for ultra high density and high speed applications

For the first time, the 65nm high performance transistor technology and the highly compacted double stacked S/sup 3/ SRAM cell with a size of 25F/sup 2/, and 0.16/spl mu/m/sup 2/ has been combined for providing the high density and high density solutions which can make the breakthrough in the field of the cache memory products and the network memory products. The SSTFT (single-crystal silicon thin film transistor) is used not only for cell transistors but also for peripheral transistors. The selective Co silicidation techniques is developed for low resistance. By utilizing this technology, the high performance 288Mb synchronous SRAM product will be fabricated.

High Density and Ultra-Low Power Mobile SRAM Using the Novel Double S3 (Stacked Single-crystal Silicon) Technology and KrF lithography

The novel mobile SRAM was developed using the double stack S technology and KrF lithography for high density and low power mobile applications. The load PMOS and pass NMOS transistors of the SRAM cell were stacked on the planar pull-down NMOS transistors in different levels, respectively, and the cell transistors were also connected in a cross-coupled way by a single node contact to reduce the cell size. The highly manufacturable 64M bit Mobile SRAM was fabricated with this technology Introduction There are great demands of high density and low power consumption for mobile applications. In order to meet the demand of higher density, the Pseudo SRAM (PSRAM) based on DRAM (Dynamic Random Access Memory) cell structure has started replacing the conventional 6T full CMOS SRAM as a RAM memory of the handheld mobile phones. Recently, in order to reduce the cell area of 6T full CMOS SRAM from 80~100F cell area to 45 F as shown in Fig.1, the single stack S SRAM cell technology has been invented. Nevertheless, the s ingle stack S SRAM cell is not small enough to compete with the pseudo SRAM in the cost and the density [1]. Therefore, the double stacked S SRAM cell as shown in Fig.2 was needed to be comparable to the chip size and the density of the Pseudo SRAM [2]. Also, 100nm KrF lithographic tools were adopted to minimize the investment and the extendibility of the KrF based patterning technology for the productivity and the cost of the mobile SRAM products. In this study, the highly manufacturable Mobile SRAM, which can be operated even at 1.3V, is fabricated with the 25F smallest SRAM cell, KrF lithography, novel crystallization method and multi layer interconnection technology. Process Technology In the double S SRAM cell of Fig.2, the pass transistor is stacked on the load PMOS transistor already stacked on the bulk pull-down NMOS transistor. The top view SEM image of the active region and the pull down transistor on the first level is shown in Fig. 3(a). The plasma nitrided gate oxide of 3.5nm was grown to reduce the thermal budget to suppress the short channel effect of CMOS transistors. After forming the planar transistor on the bulk, the high-density plasma (HDP) oxide was deposited. After inter gate dielectric (IGD) layers were planarized, the crystallized single crystal silicon thin film layer was formed as a active layer of the load PMOS transistor. Then, the load pMOS SSTFT (Stacked Singlecrystal Thin Film Transistor) was fabricated on the IGD layers, as shown in Fig. 3(b). The pass transistor on third level of the double S cell, is shown in Fig.3(c). The wordline, which is the gates of the pass transistors, is connected throughout the whole row of the cell array. Patterning of the word lines is one of the most difficult part of the S cell integration. In addition to forming the SSTFT, the other key factor in process integration of S cell was to form the node contact holes. In the S SRAM cell, the local interconnection layers for cross coupling of nodes and gates are eliminated because all nodes and gates of the transistors are connected with one contact hole which is aligned vertically through the whole layers from the node of the pass transistor on third level to the node of the pull down transistor on the bulk silicon, as shown in Fig.4. The function of through node contact is very important since only one contact has to connect all of the nodes and the gates placed on the different levels. After the node contacts are filled with W plug. The Wdamascene line for the power lines, such as Vss and Vdd, and Al metal lines as bit-line were formed to complete the memory cell structure. The vertical TEM images of the double S SRAM cell array were presented in Fig.4. Electrical Characteristics The node contact has five different contacting parts which connect between the nodes of the cell. Therefore, it has five values of the resistance. It is important to control all of the contact resistance precisely. They are very sensitive to the process conditions, such as the doping concentrations of the gates and actives and the size of the contacted area. By optimizing the process conditions, good distributions of the resistance of each contact part have been obtained as shown in Fig.6. The drive currents of 15uA/um and 2uA/um for NMOS pass SSTFT and PMOS load SSTFT were achieved with <1pA of off-state transistor leakage current, respectively (Fig.6). The distributions of stand-by current of the 64M bit Mobile SRAM are shown in Fig.7. The SNM (Static Noise Margin) of the cell are measured in Fig.8. The SNM curve shows stable margins at operation voltages. The margin was about 200mV at 1.2V. The random access time (tAA) was less than 35nsec (Fig.9) at 85°C, Vdd = 1.65V. These performance are much better than those of the Pseudo RAM and the conventional 6T full CMOS low power SRAM. Fig.10 shows the photograph of 64M bit Mobile SRAM chip fabricated with this technology. Summary High density and low power Mobile SRAM with the smallest 25F S SRAM cell was successfully fabricated by using double S technology and KrF lithography. The difficulties of the formation of the node contact, which connects various nodes and gates by side wall contacting and shared contacting schemes, was overcome by optimization of doping concentration of S/D and multi contact etching process