Byung-Chul Jeon

Buried air gap structure for improving the breakdown voltage of SOI power MOSFET's

A novel SOI power MOSFET employing a buried air gap structure (BAGS) is proposed and verified by numerical simulation. Higher breakdown voltage is achieved in proposed structure than conventional ones, because the buried air gap reduces the vertical electric field near the drain junction efficiently. It is shown that the drain-substrate capacitance is reduced due to the low dielectric constant of the buried air gap.

A probabilistic detectability-based sensor network design method for system health monitoring and prognostics:

Significant technological advances in sensing promote the use of large sensor networks to monitor engineered systems, identify damages, and quantify damage levels. Prognostics and health management technique has been developed and applied for a variety of safety-critical engineered systems, given the critical needs of system health state awareness. The prognostics and health management performance highly relies on real-time sensory signals that convey system health–relevant information. Designing an optimal sensor network with high detectability of system health state is thus of great importance to the prognostics and health management performance. This article proposes a generic sensor network design framework using a detectability measure while accounting for uncertainties in material properties and geometric tolerances. Our contributions in this article are threefold: (1) the definition of a detectability measure to quantify the diagnostic/prognostic performance of a given sensor network, (2) the development of detectability analysis based on physics-based simulation and health state classification, and (3) the formulation of a generic sensor network design optimization problem as a mixed integer nonlinear programming. We employ the genetic algorithms to solve the sensor network design optimization problem. The merit of the proposed methodology is demonstrated with a power transformer system, which suffers from core and winding joint loosening due to consistent vibration.

P-4: Electro Static Discharge Effects on Polysilicon TFTs for AMLCD

We have investigated the degradation and failure of poly-Si thin film transistors (TFT) due to electro static discharge (ESD) stress by using transmission line pulser (TLP) test. Experimental results show that degradations caused by ESD stress on the drain pad are classified into three failure modes depending on the strength of ESD stress;degradation regime, partial failure regime and complete failure regime. DC stress test has been performed to compare with the ESD stress test.

A new fault protection circuit of 600V PT-IGBT for the improved avalanche energy employing the floating p-well

A fault protection circuit, which detects over-voltage under short circuit fault, of IGBT for the improved undamped inductive switching (UIS) capability using floating p-well is proposed and fabricated. Experimental results show that the proposed circuit successfully exhibits the reduction of collector current under fault condition when the protection circuit detects the fault signal and immediately lowers gate voltage. We have also verified the operation of the proposed circuit and device by employing the measurement under hard switching fault (HSF) and fault under load (FUL) conditions and two-dimensional mixed-mode simulation.

A new protection circuit for high-voltage current saturation of LEST

A new protection circuit for high-voltage current saturation of a lateral emitter switched thyristor (LEST) is proposed. We fabricated this circuit by employing a widely used insulated gate bipolar transistor compatible process. A high-voltage current saturation exceeding 200 V was measured in the EST with the proposed protection circuit, while the current saturation of the conventional LEST is limited to 17 V by the breakdown of the lateral MOSFET.

A New 600 V Punch Through-Insulated Gate Bipolar Transistor with the Monolithic Fault Protection Circuit Using the Floating p-Well Voltage Detection

A new fault sensing scheme of the insulated gate bipolar transistor (IGBT) employing the floating p-well, which detects the over-voltage of the floating p-well under the short circuit fault condition, is proposed and implemented by fabricating the main IGBT and gate voltage pull-down circuit using the widely used planar IGBT process. The floating p-well structure also improves the avalanche energy of IGBT in addition to detecting the fault signal. The detection of fault and gate voltage pull-down operation is achieved by the proposed fault protection scheme employing the floating p-well voltage detection. The proposed fault protection circuit was measured under the hard switching fault (HSF) and fault under load (FUL) conditions. The normal switching behavior of the main IGBT with the proposed protection circuit was also investigated under inductive load switching conditions.

A new protective circuit to improve short-circuit withstanding capability of a lateral emitter switched thyristor

A new circuit to protect lateral emitter switched thyristors (LESTs) for high voltage current saturation is proposed. We fabricated this circuit by employing a widely used process compatible with insulated gate bipolar transistors (IGBTs). When the floating n+ voltage is larger than the threshold voltage of protecting metal oxide semiconductor field effect transistor (MOSFET), the protective circuit alters the operation of the LEST from regenerative mode to non-regenerative mode. Experimental results showed that a high voltage current saturation exceeding 200 V was measured in the LEST with the proposed protective circuit, while the current saturation of the conventional LEST was limited to 17 V. This allowed the LEST to withstand the hard switching fault (HSF) condition over 10 µs during the hard switching fault (HSF) condition.

Second Breakdown of 18V Grounded Gate NMOS induced by the Kirk Effect under Electrostatic Discharge

Electrostatic Discharge (ESD) failure mechanisms of 18V grounded gate NMOS (GGNMOS) for liquid crystal display driver IC (LDI) applications are investigated and effects of layout design parameters on the ESD immunity level are analyzed. Experimental results show that 18V GGNMOS exhibits snapback characteristics and the ESD immunity level is rather high when XO (N-drift overlap over n+ source/drain) is sufficiently large, while GGNMOS does not exhibit the sustaining region and is very vulnerable to ESD stress when XO is relatively small. Simulation results show that the ESD failure mechanism of 18V GGNMOS could be the low-temperature second breakdown induced by the Kirk effect. It is inferred that a certain amount of XO is indispensable to ensure snapback characteristics and high ESD immunity level. Simulation results also show that the ESD immunity level is increased as drain contact to gate space (DCGS) is increased.

A New 1200 V Punch Through-Insulated Gate Bipolar Transistor with Protection Circuit Employing Lateral Insulated Gate Bipolar Transistor and Floating p-Well Voltage Sensing Scheme

A new 1200 V punch through-insulated gate bipolar transistor (PT-IGBT) with a protection circuit employing a lateral IGBT (LIGBT) and a floating p-well voltage sensing scheme is proposed and implemented by fabricating the main IGBT and gate voltage pull-down circuit using the widely used planar IGBT process. The detection of the fault and gate voltage pull-down operations is achieved using the floating p-well sensing scheme. The LIGBT used as a pull-down transistor reduces the area of the protection circuit due to the enhanced current handling capability. The voltage saturation effect of a floating p-well voltage under the high voltage condition provides the 1200 V PT-IGBT with a reliable and rapid protection by preventing the gate oxide failure of the pull-down LIGBT and eliminating the blanking filter.

Enhanced short-circuit withstanding capability of the emitter switched thyristor (EST) by employing a new protection circuit

A new protection circuit, which improves the short-circuit withstanding capability of an emitter switched thyristor (EST) is proposed and fabricated. Experimental results show that the EST employing the protection circuit exhibits a high voltage current saturation when the protection circuit reduces the gate voltage. We have also investigated the mechanism by employing two-dimensional simulation.