Yearn-Ik Choi

Latch-up Suppressed Insulated Gate Bipolar Transistor by the Deep p^+ Ion Implantation under the n^+ Source

A novel insulated gate bipolar transistor (IGBT) structure, which employs the self aligned deep p+ buried region enveloping all the area under the n+ source, is proposed and verified by SUPREM IV and PISCES-IIB simulation. The simulation results show that the latch-up current is found to increase up to about 10 times compared with the conventional structure when the implantation dose of the p+ buried region and the p-body are 1×1015 cm-2 and 1×1014 cm-2, respectively. The variation of the threshold voltage is within 0.1 V although the implantation dose of the p+ buried region increases from 1×1014 cm-2 to 1×1015 cm-2.

Optimum design for minimum on-resistance of low voltage trench power MOSFET

An optimum trench width for the minimum on-resistance of a trench MOSFET (T-MOS) is determined analytically with the resistance contribution from the accumulation layer taken into account. Inclusion of the accumulation resistance is shown to be indispensable to the on-resistance of the T-MOS especially for a relatively large value of the trench width. The analytical results show a fair agreement with the numerical simulations using ATLAS.

Numerical analysis on the LDMOS with a double epi-layer and trench electrodes

Abstract We proposed a new lateral double-diffused MOS (LDMOS) structure employing a double p/n epitaxial layer, which is formed on p− substrates. Trenched gate and drain are also employed to obtain uniform and high drift current density. The breakdown voltage and the specific on-resistance of the proposed LDMOS are numerically calculated by using a two-dimensional (2D) device simulator, Medici . The n− drift region and upper p− region of the proposed LDMOS are fully depleted in off-states employing the RESURF technique. The simulation results show that the breakdown voltage is 142xa0V and specific on-resistance is 183xa0mΩxa0mm2 when the cell pitch of the LDMOS is 7.5xa0μm. The proposed LDMOS shows better trade-off characteristics than the previous results.

Linearly-graded surface-doped SOI LDMOSFET with recessed source

Abstract A surface-doped SOI (Silicon-On-Insulator) LD (Lateral Double-diffused) MOSFET with a linearly-graded surface-doping profile is proposed which allows low on-resistance and high static and on-state breakdown voltage. The characteristics of the proposed LDMOS are verified by the two-dimensional process simulator TSUPREM4 and the device simulator, MEDICI. A reduction of the on-resistance by 83.4% from 62.9 Ω cm to 10.4 Ω cm and an increase in the static breakdown voltage from 146 V to 205 V and in the on-state breakdown voltage from 42 V to 96 V for a 10 V gate voltage are obtained for the proposed device when compared with those of the conventional one.

Dual-gate shorted-anode LIGBT with p/sup +/ injector eliminating the negative resistance regime

A new shorted-anode lateral IGBT with dual gate and p/sup +/ injector (DG-SALIGBT) is proposed and fabricated in order to eliminate the negative differential resistance (NDR) regime, which is the inherent characteristic of SALIGBTs, by modulating the drift region conductivity gradually. The experimental results show that the NDR regime is eliminated completely and the forward voltage drop is reduced considerably in the DG-SALIGBT when compared with the conventional SALIGBT, without sacrificing the switching speed. We have analyzed the device operation mechanism, such as hole injection phenomena, by 2D numerical simulation.

Optimum design of the field plate in the cylindrical p+n junction: analytical approach

Analysis of the breakdown voltage in the p+n junction with the field plate is presented for an optimum design. The breakdown voltage is analyzed by employing the approximated electric field and breakdown path in terms of the field plate parameters and the applied reverse bias. The optimum values for oxide thickness and the field plate width are derived by the use of the breakdown voltage. The calculated breakdown voltages agree well with the experimental data and two-dimensional numerical simulation result.

Improved trench MOS barrier Schottky (TMBS) rectifier

An improved trench MOS barrier Schottky (TMBS) rectifier is proposed which utilizes the upper half of the trench sidewall as an active area. The proposed structure improves the forward voltage drop by 20% in comparison with the conventional one without degradation in breakdown voltage. The reverse leakage current is also increased by several times. An analytical model for the field distribution is given to explain the increase of the leakage current and compared with two-dimensional numerical simulations.

ANALYTICAL SOLUTION OF THE BREAKDOWN VOLTAGE FOR 6H-SILICON CARBIDE P+N JUNCTION

An analytical solution of the breakdown voltage for 6H‐silicon carbide p+n junction has been derived by employing an effective ionization coefficient. The breakdown voltage extracted from our analytical model agrees fairly well with the experimental data in the range of 1016–1018 cm−3 doping levels.

Breakdown voltage and on-resistance of multi-RESURF LDMOS

The breakdown voltage and on-resistance of a multi-RESURF LDMOS are studied numerically and analytically. The results are compared with those from the conventional LDMOS. Reduction of on-resistance by 23% is obtained for the multi-layer structure without degradation in the breakdown voltage. An analytical expression for the surface potential distribution of the multi-layer structure is derived which provides a useful mean to determine the breakdown voltage analytically in terms of the device parameters.

Numerical analysis of SOI LDMOS using a recessed source and a trench drain

Abstract A new SOI LDMOS using a recessed source and a trench drain was proposed to improve the on-characteristics at a given breakdown voltage. On-resistance and breakdown voltages of the proposed LDMOS are investigated by the two-dimensional simulator, MEDICI. The simulation results show that the on-resistance of the proposed and the conventional LDMOS are 76.3 and 129.5xa0m Ω xa0mm 2 , respectively. The on-resistance of the proposed LDMOS decreases by 41% compared to that of the conventional LDMOS at the same breakdown voltage of 36.5xa0V.