In-Hwan Ji

The first demonstration of symmetric blocking SiC gate turn-off (GTO) thyristor

This paper reports the development of symmetric blocking SiC p-GTO thyristors. The proposed thyristor structure features a positive bevel edge termination implemented by orthogonal dicing technique. In this paper, a detailed design of the device structure, forward current-voltage characteristics, and symmetric blocking capabilities are discussed.

High voltage AlGaN/GaN HFET employing low taper angle field-plate for stable forward blocking capability

A new high voltage AlGaN/GaN heterojuction field effect transistor (HFET) employing low taper angle field-plate (LTA-FP) has been proposed and verified experimentally to achieve stable forward blocking capability with low leakage current. Proposed device with a LTA-FP of 10 degrees, fabricated by adopting a new taper etching process, exhibits stable forward blocking capability with low leakage current (2 orders of magnitude smaller) under repetitive high voltage stress, whereas the conventional device with steep FP of 70 degree shows that unstable behavior under the same stress. These experimental results indicate that the proposed LTA-FP suppresses the electric field concentration at the gate edge successfully and is an effective approach to secure the stable blocking characteristics of GaN based high voltage devices.

A New Silicon-on-Insulator Lateral Insulated Gate Bipolar Transistor and Lateral Diode Employing the Separated Schottky Anode for a Power Integrated Circuit

A new silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) and lateral diode employing the separated Schottky anode (SSCA) is proposed and verified by the two dimensional numerical simulation based on experimental results. The Schottky barrier between the aluminum and lightly doped n-type silicon (Al/n-Si) of SSCA provides the potential difference between the n- anode contact and p+ anode to enhance the hole injection of p+ anode, which improves the forward current–voltage (I–V) characteristics. The anode region of SSCA-LIGBT is successfully decreased without negative differential resistance (NDR) regime and sacrificing the switching speed by employing contact. The SSCA structure applied to the diode also considerably improves the reverse recovery compared to the conventional p–i–n diode and reverse blocking capability compared to conventional Schottky diode.

Experimental Study on Improving Unclamped Inductive Switching Characteristics of the New Power Metal Oxide Semiconductor Field Effect Transistor Employing Deep Body Contact

A new power metal oxide semiconductor field effect transistor (MOSFET) with deep body contact (DBC), which improves the avalanche energy capability, is proposed and verified by experimental results. For the experiment, a 60 V, 1 A power MOSFET employing DBC has been fabricated using a complementary metal oxide semiconductor (CMOS) compatible deep Si trench process. Previous simulations show that DBC alters the direction of the current flow from the edge to the bottom of the p-body under unclamped inductive switching (UIS) conditions. DBC also suppresses the activation of the parasitic bipolar transistor due to the reduction of the current density beneath the n+ source. Experimental results show that the ruggedness of the proposed power MOSFET is improved without sacrificing any other electrical characteristics and increasing device area.

An Improved Junction Termination Design Employing Shallow Trenches and Field Limiting Rings for Power Devices

A new junction termination method employing shallow trenches filled with silicon dioxide and field limiting rings (FLRs) for 1200 V power device applications is proposed to decrease the junction termination area without sacrificing the breakdown voltage and any additional fabrication processes. The proposed structure was analyzed and verified by numerical simulations and experiments. The two-dimensional numerical simulation results show that two electric field peaks between the field limiting rings appear in the proposed structure due to the shallow trench filled with silicon dioxide while the conventional FLR structure shows a single electric field peak between the field limiting rings. The proposed structure achieves a uniform electric field distribution and increases a breakdown voltage. The junction termination area of the proposed structure is decreased at the same breakdown voltage due to the low dielectric constant of the silicon dioxide in the trench. The experimental results show that the junction termination length of the proposed structure is 15–21% lower than that of the conventional FLR. The proposed structure achieves the high breakdown voltage, which is 80% of the ideal parallel-plane junction breakdown voltage.

A New 600 V Punch Through-Insulated Gate Bipolar Transistor with the Monolithic Fault Protection Circuit Using the Floating p-Well Voltage Detection

A new fault sensing scheme of the insulated gate bipolar transistor (IGBT) employing the floating p-well, which detects the over-voltage of the floating p-well under the short circuit fault condition, is proposed and implemented by fabricating the main IGBT and gate voltage pull-down circuit using the widely used planar IGBT process. The floating p-well structure also improves the avalanche energy of IGBT in addition to detecting the fault signal. The detection of fault and gate voltage pull-down operation is achieved by the proposed fault protection scheme employing the floating p-well voltage detection. The proposed fault protection circuit was measured under the hard switching fault (HSF) and fault under load (FUL) conditions. The normal switching behavior of the main IGBT with the proposed protection circuit was also investigated under inductive load switching conditions.

A new protective circuit to improve short-circuit withstanding capability of a lateral emitter switched thyristor

A new circuit to protect lateral emitter switched thyristors (LESTs) for high voltage current saturation is proposed. We fabricated this circuit by employing a widely used process compatible with insulated gate bipolar transistors (IGBTs). When the floating n+ voltage is larger than the threshold voltage of protecting metal oxide semiconductor field effect transistor (MOSFET), the protective circuit alters the operation of the LEST from regenerative mode to non-regenerative mode. Experimental results showed that a high voltage current saturation exceeding 200 V was measured in the LEST with the proposed protective circuit, while the current saturation of the conventional LEST was limited to 17 V. This allowed the LEST to withstand the hard switching fault (HSF) condition over 10 µs during the hard switching fault (HSF) condition.

A New 1200 V Punch Through-Insulated Gate Bipolar Transistor with Protection Circuit Employing Lateral Insulated Gate Bipolar Transistor and Floating p-Well Voltage Sensing Scheme

A new 1200 V punch through-insulated gate bipolar transistor (PT-IGBT) with a protection circuit employing a lateral IGBT (LIGBT) and a floating p-well voltage sensing scheme is proposed and implemented by fabricating the main IGBT and gate voltage pull-down circuit using the widely used planar IGBT process. The detection of the fault and gate voltage pull-down operations is achieved using the floating p-well sensing scheme. The LIGBT used as a pull-down transistor reduces the area of the protection circuit due to the enhanced current handling capability. The voltage saturation effect of a floating p-well voltage under the high voltage condition provides the 1200 V PT-IGBT with a reliable and rapid protection by preventing the gate oxide failure of the pull-down LIGBT and eliminating the blanking filter.