Byung-Do Yang

A Low Power Phase-Change Random Access Memory using a Data-Comparison Write Scheme

A low power PRAM using a data-comparison write (DCW) scheme is proposed. The PRAM consumes large write power because large write currents are required during long time. At first, the DCW scheme reads a stored data during write operation. And then, it writes an input data only when the input and stored data are different. Therefore, it can reduce the write power consumption to a half. The 1K-bit PRAM test chip with 128times8bits is implemented with a 0.8mum CMOS technology with a 0.5mum GST cell.

Flexible Complementary Logic Gates Using Inkjet-Printed Polymer Field-Effect Transistors

High-performance inkjet-printed top-gate/bottom-contact organic field-effect transistors (OFETs) and complementary electronic circuitry are reported. Blends of poly(vinylidenefluoride-trifluoroethylene) (P(VDF-TrFE)) and poly(methyl methacrylate) (PMMA) dielectrics effectively reduce the operation voltage. At the optimized blend ratio of 7 : 3 wt.% for P(VDF-TrFE) and PMMA, both p- and n-type printed OFETs show well-balanced high field-effect mobility values (~ 0.5 cm2/V·s) and low threshold voltages ( ±5 V). The high-performance inverters and various digital logic gates such as nand, nor, or, and xor are demonstrated on flexible plastic substrates. The inverter shows a high gain (>; 25), an ideal inverting voltage near half of the supplied bias (1/2VDD), and a high noise immunity (up to 79 % of 1/2VDD).

A Low Power Content Addressable Memory Using Low Swing Search Lines

This paper proposes a low power content addressable memory (CAM) using low swing search lines. The CAM reduces the swing voltage and the power consumption of the search lines by using CAM cells as amplifiers. The CAM cells compare the stored data with the low swing search data on the search lines. The CAM also reduces the power consumption of match lines by using low swing NAND-NOR match lines. The 128 × 144 bit CAM chip was fabricated using a 0.18 μm CMOS process with VDD = 1.8 V. The CAM chip dissipates 2.82 fj/bit/search and consumes 8.7% of the power used by a conventional dynamic NOR-type CAM. It saves 83.9% and 97.3% of the power in the search lines and the match lines, respectively. Its area is 1.14 mm2. Its maximum operating frequency is 210 MHz.

An accurate current reference using temperature and process compensation current mirror

In this paper, an accurate current reference using temperature and process compensation current mirror (TPC-CM) is proposed. The temperature independent reference current is generated by summing a proportional to absolute temperature (PTAT) current and a complementary to absolute temperature (CTAT) current. The temperature coefficient and magnitude of the reference current are influenced by the process variation. To calibrate the process variation, the proposed TPC-CM uses two binary weighted current mirrors which control the temperature coefficient and magnitude of the reference current. After the PTAT and CTAT currents are measured, the switch codes of the TPC-CM are fixed in order that the magnitude of reference current is independent to temperature. And, the codes are stored in the non-volatile memory. In the simulation, the effect of the process variation is reduced to 0.52% from 19.7% after the calibration using a TPC-CM in chip-by-chip. A current reference chip is fabricated with a 3.3V 0.35um CMOS process. The measured calibrated reference current has 0.42% variation.

A Low-Power SRAM Using Bit-Line Charge-Recycling for Read and Write Operations

This paper proposes a low-power SRAM using bit-line charge-recycling for read and write operations. The charge-recycling SRAM (CR-SRAM) reduces the read and write powers by recycling the charge in bit lines. When N bit lines recycle their charges, the swing voltage and power of bit lines are reduced to 1/N and 1/N2, respectively. The CR-SRAM utilizes hierarchical bit-line architecture to perform the charge-recycling without static noise margin degradation in memory cells. In the simulation, the CR-SRAM saves 17% read power and 84% write power compared with the conventional SRAM. A CR-SRAM chip with 4 K × 8 bits is implemented in a 0.13-μm CMOS process. It consumes 0.128-mW read power and 0.135-mW write power at fCLK = 100 MHz and VDD = 1.2 V.

250-mV Supply Subthreshold CMOS Voltage Reference Using a Low-Voltage Comparator and a Charge-Pump Circuit

This brief proposes a subthreshold CMOS voltage reference circuit, which reduces the minimum supply voltage by replacing the analog amplifier in the conventional CMOS voltage reference circuit with a low-voltage comparator, a charge-pump circuit, and a digital control circuit. The subthreshold CMOS voltage reference circuit was fabricated using a 0.11-μm CMOS process. Its core area was 0.013 mm² and it consumed 5.35 μW at V_DD = 250 mV and f_CLK = 1 MHz. Its minimum supply voltage was 242 mV. Ten sample chips generated 193-207-mV reference voltage with 0.4-3.2-mV/100-mV line sensitivity at V_DD = 250-400 mV and 58-186 ppm/°C temperature coefficient at 10 °C-90 °C.

Low-Power and Area-Efficient Shift Register Using Pulsed Latches

This paper proposes a low-power and area-efficient shift register using pulsed latches. The area and power consumption are reduced by replacing flip-flops with pulsed latches. This method solves the timing problem between pulsed latches through the use of multiple non-overlap delayed pulsed clock signals instead of the conventional single pulsed clock signal. The shift register uses a small number of the pulsed clock signals by grouping the latches to several sub shifter registers and using additional temporary storage latches. A 256-bit shift register using pulsed latches was fabricated using a 0.18 μm CMOS process with VDD=1.8V. The core area is 6600 μm2. The power consumption is 1.2 mW at a 100 MHz clock frequency. The proposed shift register saves 37% area and 44% power compared to the conventional shift register with flip-flops.

A fast-switching current-pulse driver for LED backlight

In this paper, a fast-switching current-pulse driver for light emitting diodes (LED) backlight is proposed. It uses a regulated drain current mirror (RD-CM) [1] and a high-voltage NMOS transistor (HV-NMOS). It achieves the fast-response current-pulse switching by using a dynamic gain-boosting amplifier (DGB-AMP). The DGB-AMP does not discharge the large HV-NMOS gate capacitance of the RD-CM when the output current switch turns off. Therefore, it does not need to charge the HV-NMOS gate capacitance when the switch turns on. The proposed current-pulse driver achieves the fast current switching by removing the repetitive gate discharging and charging. Simulation results were verified with measurements performed on a fabricated chip using a 5V/40V 0.5um BCD process. It reduces the switching delay to 360ns from 700ns of the conventional current-pulse driver.

A highly accurate BiCMOS cascode current mirror for wide output voltage range

In this paper, a highly accurate wide swing BiCMOS cascode current mirror is proposed. It uses the base-current compensated BJT current mirror. It increases both output impedance and output voltage range by using the npn-NMOS cascode instead of the NMOS-NMOS cascode. The npn transistor copies the input current and the NMOS transistor increases the output impedance for the accurate current mirroring. The proposed current mirror achieves highly constant current for wide output voltage range. Simulation results were verified with measurements performed on a fabricated chip using a 5/16 V 0.5 um BCD process. It has only -2.5~1.0% current error for 0.3~16 V output voltage range.

A PWM Phase-Shift Circuit using an RC Delay for Multiple LED Driver ICs

This paper proposes a PWM phase-shift circuit to make that the LED lighting system distributes the channel currents evenly for any number of LED strings by generating evenly phaseshifted PWM signals for multiple LED driver ICs. The evenly distributed channel currents reduce the peak current, the decoupling capacitor size, and EMI noise. The PWM phase-shift circuit makes an arbitrary degree of PWM phase-shift by using a resistor and a capacitor. It measures the RC delay once. It reduces the number of external resistors and capacitors by providing zero and 180 degree phaseshift modes requiring no resistor and capacitor. An LED driver IC with the PWM phase-shift circuit was fabricated with a 0.35 μm BCDMOS process. The PWM phase-shift circuit receives a PWM signal of 50 Hz~20 kHz at f CLK =450 kHz and it generates a 0~360° phase-shifted PWM signal with R=0~1.1 MΩ at C=1 nF and f PWM =1 kHz. The measured phase errors are 1.74~3.94% due to parasitic capacitances.