Hyeong-Ju Kang

A Low Power Content Addressable Memory Using Low Swing Search Lines

This paper proposes a low power content addressable memory (CAM) using low swing search lines. The CAM reduces the swing voltage and the power consumption of the search lines by using CAM cells as amplifiers. The CAM cells compare the stored data with the low swing search data on the search lines. The CAM also reduces the power consumption of match lines by using low swing NAND-NOR match lines. The 128 × 144 bit CAM chip was fabricated using a 0.18 μm CMOS process with VDD = 1.8 V. The CAM chip dissipates 2.82 fj/bit/search and consumes 8.7% of the power used by a conventional dynamic NOR-type CAM. It saves 83.9% and 97.3% of the power in the search lines and the match lines, respectively. Its area is 1.14 mm2. Its maximum operating frequency is 210 MHz.

A PWM Phase-Shift Circuit using an RC Delay for Multiple LED Driver ICs

This paper proposes a PWM phase-shift circuit to make that the LED lighting system distributes the channel currents evenly for any number of LED strings by generating evenly phaseshifted PWM signals for multiple LED driver ICs. The evenly distributed channel currents reduce the peak current, the decoupling capacitor size, and EMI noise. The PWM phase-shift circuit makes an arbitrary degree of PWM phase-shift by using a resistor and a capacitor. It measures the RC delay once. It reduces the number of external resistors and capacitors by providing zero and 180 degree phaseshift modes requiring no resistor and capacitor. An LED driver IC with the PWM phase-shift circuit was fabricated with a 0.35 μm BCDMOS process. The PWM phase-shift circuit receives a PWM signal of 50 Hz~20 kHz at f CLK =450 kHz and it generates a 0~360° phase-shifted PWM signal with R=0~1.1 MΩ at C=1 nF and f PWM =1 kHz. The measured phase errors are 1.74~3.94% due to parasitic capacitances.

Area-efficient convolutional deinterleaver for mobile TV receiver

In this article, a single-pointer structure is proposed for the convolutional deinterleavers of mobile TV receivers. To enhance the burst-error correcting capability, the convolutional interleaving and deinterleaving scheme is widely used in mobile TV receivers. However, a convolutional deinterleaver requires many pointer registers. This article introduces a single-pointer structure that reduces the number of pointer registers. Experimental results show that the single-pointer structure reduces the area of the convolutional deinterleaver by 70% in a mobile TV receiver.

Low-Power Time Deinterleaver for ISDB-T Receiver

A time deinterleaver structure for Terrestrial Integrated Services Digital Broadcasting (ISDB-T) is presented to reduce power consumption in synchronous dynamic random-access memory (SDRAM). ISDB-T exploits long time interleaving, which requires many long delay buffers at the deinterleaving of the receiver. The conventional single-pointer structure reduces the number of the pointer registers, but it shows inefficiency with SDRAM. The proposed structure allocates the delay buffers appropriately for reducing the number of SDRAM accesses and row activations and, as a result, the SDRAM power consumption. Experimental result shows that SDRAM power consumption is reduced by 24%.

Area-Efficient Prefilter Architecture for a CDMA Receiver

This brief proposes an area-efficient memory-based prefilter delay line structure. A prefilter-rake chip-level equalizer is used in a code-division multiple-access receiver to deal with multiple-access interference. A prefilter, which functions as an adaptive filter, has a sparsity property, where the number of taps with nonzero coefficients is much smaller than the number of whole taps. On the basis of the sparsity property, this brief shows how a memory device can be a reasonable candidate for a prefilter delay line. After proposing a scheme to reduce the area of the memory-based delay line, this brief shows that the proposed structure provides less area than a conventional register-based structure in typical industrial cases.