Myonglae Chu

Neuromorphic Hardware System for Visual Pattern Recognition With Memristor Array and CMOS Neuron

This paper presents a neuromorphic system for visual pattern recognition realized in hardware. A new learning rule based on modified spike-timing-dependent plasticity is also presented and implemented with passive synaptic devices. The system includes an artificial photoreceptor, a Pr0.7Ca0.3MnO3-based memristor array, and CMOS neurons. The artificial photoreceptor consisting of a CMOS image sensor and a field-programmable gate array converts an image into spike signals, and the memristor array is used to adjust the synaptic weights between the input and output neurons according to the learning rule. A leaky integrate-and-fire model is used for the output neuron that is built together with the image sensor on a single chip. The system has 30 input neurons that are interconnected to 10 output neurons through 300 memristors. Each input neuron corresponding to a pixel in a 5 × 6 pixel image generates voltage pulses according to the pixel value. The voltage pulses are then weighted and integrated by the memristors and the output neurons, respectively, to be compared with a certain threshold voltage above which an output neuron fires. The system has been successfully demonstrated by training and recognizing number images from 0 to 9.

Electronic system with memristive synapses for pattern recognition

Memristive synapses, the most promising passive devices for synaptic interconnections in artificial neural networks, are the driving force behind recent research on hardware neural networks. Despite significant efforts to utilize memristive synapses, progress to date has only shown the possibility of building a neural network system that can classify simple image patterns. In this article, we report a high-density cross-point memristive synapse array with improved synaptic characteristics. The proposed PCMO-based memristive synapse exhibits the necessary gradual and symmetrical conductance changes, and has been successfully adapted to a neural network system. The system learns, and later recognizes, the human thought pattern corresponding to three vowels, i.e. /a /, /i /, and /u/, using electroencephalography signals generated while a subject imagines speaking vowels. Our successful demonstration of a neural network system for EEG pattern recognition is likely to intrigue many researchers and stimulate a new research direction.

Oxide based nanoscale analog synapse device for neural signal recognition system

We report oxide based analog synpase for neuromorphic system. By optimizing redox reaction at the metal/oxide interface, we can obtain stable analog synapse characteristics and wafer scale switching uniformity. We have confirmed the feasibility of neuromorphic hardware system with oxide synapse array device which recognizes the electroencephalogram (EEG) signal and rats neural signal.

High density neuromorphic system with Mo/Pr0.7Ca0.3MnO3 synapse and NbO2 IMT oscillator neuron

We report novel nanoscale synapse and neuron devices for ultra-high density neuromorphic system. By adopting a Mo electrode, the redox reaction at Mo/Pr0.7Ca0.3MnO3 (PCMO) interface was controlled which in turn significantly improve synapse characteristics such as switching uniformity, disturbance, retention and multi-level data storage under identical pulse condition. Furthermore, The NbO2 based Insulator-Metal Transition (IMT) oscillator was developed for neuron application. Finally, we have experimentally confirmed the realization of pattern recognition with high accuracy using the 11k-bit Mo/PCMO synapse array and NbO2 oscillator neuron.

Analog Synapse Device With 5-b MLC and Improved Data Retention for Neuromorphic System

This letter presents an investigation of analog synapse characteristics of a PCMO-based interface switching device with varying electrode materials. In comparison with the filamentary switching device having only 1-b storage and variability issues, the interface switching devices exhibit excellent electrical properties, such as 5-b (32-level) multi-level cell characteristics, wafer-scale switching uniformity, and scalability of the switching energy with device area. To improve data retention of the interface switching device, we propose a Mo electrode to increase the oxidation barrier height (~0.4 eV) that, in turn, significantly improves the retention time and pattern classification accuracy of neural networks.

A 10-bit 200-MS/s Zero-Crossing-Based Pipeline ADC in 0.13-

This brief presents a zero-crossing-based pipeline analog-todigital converter (ADC) architecture that can effectively reduce hardware complexity and power consumption for high-speed ADCs. The ADC uses only simple open-loop amplifiers for residue amplification. Using modified sliding interpolation and subranging techniques, the number of amplifiers is reduced by 60%. A 10-bit 200-MS/s ADC, employing the architecture and other techniques, such as double sampling, digital error correction, and source degeneration, is fabricated in 0.13-μm CMOS process and occupies a die area of 0.7 mm2. The differential and integral nonlinearity of the ADC are less than 0.83/-0.47 and 1.05/-0.7 LSB, respectively. With a 1.5-MHz full-scale input, the ADC achieves 56.5-dB signal-to-noise plus distortion ratio, 71.8-dB spurious free dynamic range, and 9.1 effective number of bits at full sampling rate while dissipating 38 mW from a 1.2-V supply.

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One of the key elements in an artificial neural networks (ANNs) is the activation function (AF), that converts the weighted sum of a neurons input into a probability of firing rate. The hardware implementation of the AF requires complicated circuits and involves a considerable amount of power dissipation. This renders the integration of a number of neurons onto a single chip difficult. This paper presents circuit techniques for realizing four different types of AFs, such as the step, identity, rectified-linear unit (ReLU), and the sigmoid, based on stochastic computing. The proposed AF circuits are simpler and consume considerably lesser power than the existing ones. A handwritten digit recognition system employing the AF circuits has been simulated for verifying the effectiveness of the techniques.