Byungsub Kim

An Energy-Efficient Equalized Transceiver for RC-Dominant Channels

This work describes the architecture and circuit implementation of a high-data-rate, energy-efficient equalized transceiver for high-loss dispersive channels, such as RC-limited on-chip interconnects or silicon-carrier packaging modules. The charge-injection transmitter directly conducts pre-emphasis current from the supply into the channel, eliminating the power overhead of analog current subtraction in conventional transmit pre-emphasis, while significantly relaxing the driver coefficient accuracy requirements. The transmitter utilizes a power efficient non-linear driver by compensating non-linearity with pre-distorted equalization coefficients. A trans-impedance amplifier at the receiver achieves low static power consumption, large signal amplitude, and high bandwidth by mitigating limitations of purely-resistive termination. A test chip is fabricated in 90-nm bulk CMOS technology and tested over a 10-mm, 2- μm pitched on-chip differential wire. The transceiver consumes 0.37-0.63 pJ/b with 4-6 Gb/s/ch.

Equalized interconnects for on-chip networks: modeling and optimization framework

This paper presents a modeling framework for fast design space exploration and optimization of equalized on-chip interconnects. The exploration is enabled by cross-layer modeling that connects the transistor and wire parameters to link performance, equalization coefficients, and architecture-friendly metrics (delay, energy-per-bit, and throughput density). Appropriate models are derived to speed-up the search by more than two orders of magnitude and make a million point design space searchable in less than two hours on a standard machine. With this approach we are able to find the best link design for target throughput, power and area constraints, thus enabling the architectural optimization of energy-efficient on-chip networks. For the same latency and throughput density, equalized interconnects optimized using the new methodology have up to 10times better energy-efficiency than optimized repeater interconnects.

Characterization of Equalized and Repeated Interconnects for NoC Applications

As the number of cores increases and onand off-chip bandwidth demand rises, it is becoming increasingly more difficult to rely on conventional interconnects and remain within the chip power budget. This article explores leveraging equalization for global and semi-global long interconnects to overcome this problem.

Designing Energy-Efficient Low-Diameter On-Chip Networks with Equalized Interconnects

In a power and area constrained multicore system, the on-chip communication network needs to be carefully designed to maximize the system performance and programmer productivity while minimizing energy and area. In this paper, we explore the design of energy-efficient low-diameter networks (flattened butterfly and Clos) using equalized on-chip interconnects. These low-diameter networks are attractive as they can potentially provide uniformly high throughput and low latency across various traffic patterns, but require efficient global communication channels. In our case study, for a 64-tile system, the use of equalization for the wire channels in low-diameter networks provides 2x reduction in power with no loss in system performance compared to repeater-inserted wire channels. The use of virtual channels in routers further reduces the power of the network by 25-50% and wire area by 2x.

Power-adaptive operational amplifier with positive-feedback self biasing

This paper introduces a positive-feedback self-biasing technique for operational amplifiers (op-amps) which enables their power consumption to adapt to their environment: The power consumption of one of our op-amps scales almost linearly with load capacitance, input signal frequency, and output signal swing. Our op-amp is primarily intended for low power switched-capacitor applications. A voltage follower built in the MOSIS/AMI 0.5mum process with our op-amp has a measured power consumption that varies between 1.38muW and 90muW, as the load capacitance varies from 1pF to 100pF