John F. Bulzacchelli

A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology

This paper presents a 90-nm CMOS 10-Gb/s transceiver for chip-to-chip communications. To mitigate the effects of channel loss and other impairments, a 5-tap decision feedback equalizer (DFE) is included in the receiver and a 4-tap baud-spaced feed-forward equalizer (FFE) in the transmitter. This combination of DFE and FFE permits error-free NRZ signaling over channels with losses exceeding 30 dB. Low jitter clocks for the transmitter and receiver are supplied by a PLL with LC VCO. Operation at 10-Gb/s with good power efficiency is achieved by using half-rate architectures in both transmitter and receiver. With the transmitter producing an output signal of 1200mVppd, one transmitter/receiver pair and one PLL consume 300mW. Design enhancements of a half-rate DFE employing one tap of speculative feedback and four taps of dynamic feedback allow its loop timing requirements to be met. Serial link experiments with a variety of test channels demonstrate the effectiveness of the FFE/DFE equalization

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology

As exemplified by standards such as OIF CEI-25G, 32G-FC, and next-generation 100GbE, serial link data rates are being pushed up to 25 to 28Gb/s in order to increase I/O system bandwidth. Such speeds represent a near doubling of the state-of-the-art for fully integrated transceivers [1-3]. With scaling no longer providing large gains in device speed, significant design advances must be made to attain these data rates. This paper describes a 28Gb/s serial link transceiver featuring a source-series terminated (SST) driver topology with twice the speed of existing designs, a two-stage peaking amplifier with capacitively-coupled parallel input stages and active feedback, and a 15-tap DFE. The use of capacitive level-shifters allows a single current-integrating summer to drive the parallel paths used for speculating the first two DFE taps.

Is 25 Gb/s On-Board Signaling Viable?

What package improvements are required for dense, high-aggregate bandwidth buses running at data rates beyond 10 Gb/s per channel, and when might optical interconnects on the board be required? We present a study of distance and speed limits for electrical on-board module-to-module links with an eye to answering these questions. Hardware-validated models of advanced organic modules and printed circuit boards were used to explore these limits. Simulations of link performance performed with an internal link modeling tool allowed us to explore the effect of equalization and modulation formats at different data rates on link bit error rate and eye opening. Our link models have been validated with active, high-speed differential bus measurements utilizing a 16-channel link chip with programmable equalization and a per-channel data rate of up to 11 Gb/s. Electrical signaling limits were then determined by extrapolating these hardware-correlated models to higher speeds, and these limits were compared to the results of recent work on on-board optical interconnects.

Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout Voltage

A dual-loop architecture employs eight distributed microregulators (UREGs) to achieve load response times below 500 ps in 45-nm SOI CMOS. The trip point of an asynchronous comparator inside each UREG is tuned for high DC accuracy with a local charge pump, which receives UP/DOWN currents from a slow outer feedback loop. The feedback through the charge pumps also ensures balanced load sharing among the UREGs. Two techniques are introduced to reduce the output ripple generated by switching the pMOS passgate on and off: hybrid fast/slow passgate control (in which the DC portion of the load current is supplied by a parallel output device with slew-rate-limited gate drive) and pMOS strength calibration (which adjusts the active width of the passgate to compensate for PVT variations). The distributed regulator system is integrated into a DDR3 I/O core and supplies power to CMOS delay lines used for clock-to-data deskewing. Each of the eight UREGs is sized to provide up to 5.3 mA of load current and occupies an area of 55 × 60 μm2. The measured DC load regulation is better than 10 mV down to an 85-mV dropout voltage. Jitter readings of the CMOS delay lines indicate output noise close to 28 mVpp.

5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8 TM microprocessor

Integrated voltage regulator modules (iVRMs) [1] provide a cost-effective path to realizing per-core dynamic voltage and frequency scaling (DVFS), which can be used to optimize the performance of a power-constrained multi-core processor. This paper presents an iVRM system developed for the POWER8™ microprocessor, which functions as a very fast, accurate low-dropout regulator (LDO), with 90.5% peak power efficiency (only 3.1% worse than an ideal LDO). At low output voltages, efficiency is reduced but still sufficient to realize beneficial energy savings with DVFS. Each iVRM features a bypass mode so that some of the cores can be operated at maximum performance with no regulator loss. With the iVRM area including the input decoupling capacitance (DCAP) (but not the output DCAP inherent to the cores), the iVRMs achieve a power density of 34.5W/mm2, which exceeds that of inductor-based or SC converters by at least 3.4× [2].

A 7Gb/s 9.3mW 2-Tap Current-Integrating DFE Receiver

A 7Gb/s 2-tap current-integrating DFE implemented in a 90nm CMOS process is presented. Low power dissipation (9.3mW) is achieved by replacing resistively loaded analog current summers with resettable integrators. With 7Gb/s PRBS-7 data, the input sensitivity is 61 mVpp-diff, and the DFE equalizes a 16-inch backplane with 45% horizontal eye opening. The DFE core (integrators, latches, clock buffers) occupies 85 times 65mum2.

A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS

This paper presents the design of a 19-Gb/s serial link receiver with both 4-tap feed-forward equalizer (FFE) and 5-tap decision-feedback equalizer (DFE), thereby making the equalization system self-contained in the receiver. This design extends existing power-efficient DFEs based on current-integrating summers and adds FFE functionality to the DFE circuit infrastructure for an efficient implementation. Key techniques for implementing receive-side FFE are: the use of multiphase quarter-rate sample-and-hold circuits for generating multiple time-shifted input data signals, time-based analog multiplication for FFE coefficient weighting, and a merged FFE/DFE summer. The receiver test chip, implemented in a 45-nm silicon-on-insulator (SOI) CMOS technology, occupies 0.07 mm2 and has a power efficiency of 6.2 mW/Gb/s at 19 Gb/s. Step-reponse characterization of the receiver demonstrates accurate FFE computation. The receiver equalizes a 35-in PCB trace at 17 Gb/s with a channel loss of 30 dB at 8.5 GHz and a 20-in PCB trace at 19 Gb/s with a channel loss of 25 dB at 9.5 GHz.

An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects

A source synchronous I/O system based on high-density silicon carrier interconnects is introduced. Benefiting from the advantages of advanced silicon packaging technologies, the system uses 50 μm-pitch μC4s to reduce I/O cell size and fine-pitch interconnects on silicon carrier to achieve record-breaking interconnect density. An I/O architecture is introduced with link redundancy such that any link can be taken out of service for periodic recalibration without interrupting data transmission. A timing recovery system using two phase rotators shared across all bits in a receive bus is presented. To demonstrate these concepts, an I/O chipset using this architecture is fabricated in 45 nm SOI CMOS technology. It includes compact DFE-IIR equalization in the receiver, as well as a new all-CMOS phase rotator. The chipset is mounted to a silicon carrier tile via Pb-free SnAg μ C4 solder bumps. Chip-to-chip communication is achieved over ultra-dense interconnects with pitches of between 8 μm and 22 μm. 8 × 10-Gb/s data is received over distances up to 4 cm with a link energy efficiency of 5.3 pJ/bit from 1 V TX and RX power supplies. 8 × 9-Gb/s data is recovered from a 6-cm link with 16.3 dB loss at 4.5 GHz with an efficiency of 6.1 pJ/bit.

Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications

Wireline communication applications typically require a low-phase-noise wide-tuning-range PLL. While these requirements can be met using traditional charge-pump PLL architectures, a high-performance digital PLL (DPLL)-based solution offers potential advantages in area, testability, and flexibility. Nearly all high-performance DPLL architectures reported in the literature to date (see, e.g., [1–3]) incorporate a time-to-digital converter (TDC) that acts as the loops PFD. Subject to its quantization limits, a high-resolution TDC generates output signals proportional to the phase error at its input, effectively linearizing the PFD response. It should be noted, however, that reported high-performance TDC-based DPLLs have generally been fractional-N, i.e., not integer-N, synthesizers. In a fractional-N loop, the phase difference between the feedback clock and the reference clock at the PFD input varies significantly, frequently jumping by as much as a full output clock period from one phase comparison to the next. At 10GHz output, this results in a 100ps phase shift, thus making a TDC with resolution on the order of 10 to 20ps adequate to generate multiple quantization levels. In an integer-N case, by contrast, a PLL with 500fsrms jitter at the output and a typical feedback divider value in the range of 16 to 40 would have feedback phase jitter of only 2 to 3.2psrms. In this low noise situation, a TDC with less than 3.2ps of resolution would act essentially like a bang-bang PFD (BB-PFD). Existing wireline communication PLLs are predominantly integer-N designs with strict system-level requirements on the rms jitter. A DPLL designer targeting these applications, therefore, would have to face the challenging and ever-increasing requirements on TDC resolution, or to find a way of using a BB-PFD.

A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS

A 90nm CMOS 10Gb/s SerDes for chip-to-chip communications over backplanes is presented. To mitigate channel impairments, the RX uses a 5-tap DFE and the TX a 4-tap FIR filter. The IC equalization abilities are evaluated using different type of channels. The power consumption of one (TX, RX) pair and one PLL is 300mW for 1.2Vpp differential TX output swing