David G. Nairn

Current-mode algorithmic analog-to-digital converters

A current-mode technique for the design of algorithmic analog-to-digital converters (ADCs) is presented. The current-mode technique allows the necessary voltage swing for a given dynamic range to be reduced while at the same time eliminating the need for large capacitors on which to store the signal. Consequently, the resulting ADCs can be made very small and yet still capable of providing high sampling rates. The advantages and disadvantages of different current mirror structures for use in ADCs are discussed. Experimental results for ADCs fabricated using a 3- mu m CMOS process are reported, including an 8-b ADC which displayed a sampling rate of 500 kHz and a total circuit area of under 0.75 mm/sup 2/. >

A ratio-independent algorithmic analog-to-digital converter combining current mode and dynamic techniques

An algorithmic analog-to-digital converter (ADC) that combines current mode and dynamic techniques is presented. The converter does not rely on high-gain amplifiers or well-matched components to achieve high resolution and is inherently insensitive to the amplifiers offset voltage. An analysis of the converters limitations indicates that the resolution of practical circuits will be limited by the switch-induced charge injection. Ultimately, however, the kT/C noise leads to an area/resolution tradeoff and the transistors thermal noise leads to a speed/power tradeoff. A prototype fabricated using a 3- mu m CMOS process achieved 10-bit resolution at a sampling rate of 25 kHz on an area of only 0.18 mm/sup 2/. >

Zero-voltage switching in switched current circuits

Traditionally the accuracy of switched-current circuits has been much lower than that of switched-capacitor circuits. To address this problem, an accurate high-speed switched-current sample-and-hold technique based on zero-voltage switching is presented. The technique significantly reduces the signal dependent charge injection, leading to improved sampling accuracy. To demonstrate the proposed technique, a sample-and-hold has been implemented using a 1.2 /spl mu/m CMOS process. The circuit is expected to achieve 14 bit linearity at sampling rates exceeding 50 M Samples/sec. While dissipating only 3.5 mW from a nominal 3.3 V supply.<<ETX>>

Time-interleaved analog-to-digital converters

This paper provides a tutorial review of time-interleaved analog-to-digital converters. After explaining the impact of offset, gain, timing and other mismatches on converter performance, current solutions to the mismatch problems are presented. The paper concludes with a summary of the current-state-of-the art for time-interleaved analog-to-digital converters.

Ratio-independent current mode algorithmic analog-to-digital converters

A new ratio-independent algorithmic analog-to-digital converter, using current instead of voltage, is described. The proposed ADC (analog-to-digital converter) does not require well-matched components or high-gain amplifiers and can be made insensitive to the amplifiers offset voltage. A prototype of the proposed circuit was designed and fabricated using a 3- mu m CMOS process. The circuit occupies less than 0.2 mm/sup 2/, displays a 10-b resolution with a 25-kHz sampling rate, and operates from a single 5-V supply.<<ETX>>

A current mode algorithmic analog-to-digital converter

A novel algorithmic analog-to-digital converter (ADC), using current instead of voltage to represent the signal, is described. The use of current eliminates switch-induced errors due to charge injection and results in reasonably high sampling rates without the need for large chip areas. To test this new concept, a 6-bit converter using a 3- mu m CMOS process was fabricated. The resulting circuit occupies a sampling rate of 200 kHz while drawing only 5 mW from a single 5-V supply. The speed of the ADC was limited by the settling time of the relatively large current mirrors.<<ETX>>

Current mode analog-to-digital converters

Recent work on current mode ADCs (analog-to-digital converters) is reviewed. For comparison purposes, a brief look is taken at what has been achieved using some of the more popular voltage mode ADCs. Following this some of the reported current/voltage-mode and current-mode ADCs are discussed. Recent advances in current-mode ADCs are then reviewed to illustrate the performance that can presently be achieved using these techniques.<<ETX>>

Design and analysis of metastable-hardened and soft-error tolerant high-performance, low-power flip-flops

In this paper, detailed analysis is given on the design of metastable-hardened and soft-error tolerant flip-flops while maintaining the basic characteristics of low-power and high-performance. We also propose two new flip-flop designs: pre-discharge soft-error tolerant flip-flop (PDFF-SE) and sense-amplifier transmission-gate soft-error tolerant flip-flop (SATG-SE). Following our main design approach, both PDFF-SE and SATG-SE use a cross-coupled inverter on the critical path in the master-stage to achieve good metastability while generating differential signals to facilitate the usage of the Quatro cell in the slave-stage to protect against soft-errors. PDFF-SE is designed to achieve very high performance with good metastability while SATG-SE is a low-power design also with good metastability. We also introduce two new design metrics, namely the metastability-delay-product (MDP) and the metastability-power-delay-product (MPDP), to analyze the design tradeoffs between metastability, power, and performance. Simulation results in 65nm CMOS technology have shown that both proposed designs achieve significant reduction in MDP and MPDP when compared to other flip-flop architectures analyzed in this work. Monte Carlo simulation results also show that these flip-flops are very robust and reliable against process variations and mismatches.

Design and analysis of metastable-hardened flip-flops in sub-threshold region

Flip-flop metastability is becoming an important consideration for designing reliable synchronous and asynchronous systems, especially in the sub-threshold region where it degrades exponentially with the reduction in supply voltage. In this paper, detailed analysis is given on the design of metastable-hardened flip-flops in the sub-threshold region. Proper transistor sizing using either transconductance or load variation along with implementing the inverter pair in the flip-flop master-stage with low-Vth can result in significant reduction in the time-resolving constant τ. Extensive simulation results have shown that the optimum metastability-power-delay-product (MPDP) design allows the flip-flops to improve its metastability with a more balanced design tradeoff between performance and power consumption.

An Energy-Efficient Offset-Cancelling Sense Amplifier

As SRAM cells are scaled aggressively to increase the overall packing density, the smaller transistors exhibit higher degrees of process variation and mismatch, leading to larger offset voltages. For SRAM sense amplifiers (SAs), higher offset voltages lead to an increased likelihood of an incorrect decision. In this brief, an SA capable of cancelling the input offset voltage is presented. The simulated and measured results in 180-nm technology show that the SA is capable of detecting a 4-mV differential input signal under dc and transient conditions. The proposed SA when compared with other offset cancellation schemes exhibits comparable offset cancellation performance with a smaller delay and significantly lower energy consumption.