C. Alexander

Random-Dopant-Induced Drain Current Variation in Nano-MOSFETs: A Three-Dimensional Self-Consistent Monte Carlo Simulation Study Using “ Ab Initio ” Ionized Impurity Scattering

A comprehensive simulation study of random-dopant-induced drain current variability is presented for a series of well-scaled n-channel MOSFETs representative of the 90-, 65-, 45-, 35-, and 22-nm technology nodes. Simulations are performed at low and high drain biases using both 3-D drift diffusion (DD) and 3-D Monte Carlo (MC). The ensemble MC simulator incorporates an ldquo ab initiordquo treatment of ionized impurity scattering through the real-space trajectories of the carriers in the Coulomb potential of the random discrete impurities. When compared with DD simulations, the MC simulations reveal a significant increase in the drain current variability as a result of additional transport variations due to position-dependent Coulomb scattering that is not captured within the DD mobility model. Such transport variations are in addition to the electrostatic variation in carrier density that is alone captured within the DD approach. Through comparison of the DD and MC results, we estimate the relative importance of electrostatic and transport-induced variability at different drain bias conditions.

Advanced simulation of statistical variability and reliability in nano CMOS transistors

Increasing CMOS device variability has become one of the most acute problems facing the semiconductor manufacturing and design industries at, and beyond, the 45 nm technology generation. Most problematic of all is the statistical variability introduced by the discreteness of charge and granularity of matter in transistors with features already of molecular dimensions [i]. Two transistors next to each other on the chip with exactly the same geometries and strain distributions may have characteristics from each end of a wide statistical distribution. In conjunction with statistical variability [ii], negative bias temperature instability (NBTI) and/or hot carrier degradation can result in acute statistical reliability problems. It already profoundly affects SRAM design, and in logic circuits causes statistical timing problems and is increasingly leading to hard digital faults. In both cases, statistical variability restricts supply voltage scaling, adding to power dissipation problems [iii]. In this invited paper we describe recent advances in predictive physical simulation of statistical variability using drift diffusion (DD), Monte Carlo (MC) and quantum transport (QT) simulation techniques.

3-D Monte Carlo Simulation of the Impact of Quantum Confinement Scattering on the Magnitude of Current Fluctuations in Double Gate MOSFETs

For the scaling of ultrathin body double gate (UTB DG) MOSFETs to channel lengths below 10 nm, a silicon body thickness of less than 5 nm is required. At these dimensions the influence of atomic scale roughness at the interface between the silicon body and the gate dielectric becomes significant, producing appreciable body thickness fluctuations. These fluctuations result in a scattering potential related to the quantum confinement variation within the channel which, similarly to the interface roughness scattering, influences the mobility, the drive current and the intrinsic parameter variations. In this paper we have developed an ensemble Monte Carlo simulation approach to study the impact of quantum confinement scattering on the transport in sub-10 nm UTB DG MOSFETs, and the corresponding intrinsic parameter variations. By comparing the Monte Carlo simulations with drift-diffusion simulations we quantify the important contribution of the quantum confinement related scattering to the current fluctuations in such devices

Impact of single charge trapping in nano-MOSFETs-electrostatics versus transport effects

In this paper, using Monte Carlo (MC) simulations featuring ab initio Coulomb scattering, we study the impact of Coulomb scattering from a single trapped electron on the magnitude of the corresponding drain-current reduction in a series of well scaled n-channel nano-MOSFETs. Through a careful comparison with drift-diffusion (DD) simulations that only capture the electrostatic effects associated with the trapped charge, we were able to demonstrate the specific contribution of the scattering. The simulations are performed at low drain bias for MOSFETs with channel lengths of 30, 20, and 10 nm, respectively. Compared to the DD results, the MC simulations show significant additional reduction in drain current associated with the scattering from the trapped electron. The scattering related percentage reduction in the current increases with the increase of the gate voltage toward strong inversion conditions. The velocity distributions in the presence of the trapped charge at various gate conditions are carefully analyzed in order to explain the magnitude of the observed effect.

Variability Aware Simulation Based Design- Technology Cooptimization (DTCO) Flow in 14 nm FinFET/SRAM Cooptimization

In this paper, we use an automated tool flow in a 14 nm CMOS fin-shaped field-effect transistor (FinFET)/ static random access memory (SRAM) simulation-based design-technology cooptimization (DTCO) including both process-induced and intrinsic statistical variabilities. A 22 nm FinFET CMOS technology is used to illustrate the sensitivity to process-induced fin shape variation and to motivate this paper. Predictive Technology Computer Aided Design (TCAD) simulations have been carried out to evaluate the transistor performance ahead of silicon. Draft-diffusion simulations calibrated to the ensemble Monte Carlo simulation results are used to explore the process and the statistical variability space. This has been enabled by the automation of the tool flow and the dataset handling. The interplay between the process and the statistical variability has been examined in details. A two-stage compact model strategy is used to capture the interplay between process and statistical variability. To close the DTCO loop, the static noise margin and write noise margin sensitivity to cell design parameters and variability in FinFET-based SRAM designs are studied in details.

Random Impurity Scattering Induced Variability in Conventional Nano-Scaled MOSFETs: Ab initio Impurity Scattering Monte Carlo Simulation Study

Results of statistical 3D Monte Carlo (MC) simulation of random dopant induced current variations are presented for a series of well-scaled nano-MOSFETs. Comparison is made with drift diffusion (DD) results showing an increase in the estimated current variation. This is associated with additional transport variation that has been included within the MC

Simulation based transistor-SRAM co-design in the presence of statistical variability and reliability

We report on a systematic simulation study of the impact of process and statistical variability and reliability on SRAM cell design in a 14nm technology node SOI FinFET transistors. A comprehensive statistical compact modelling strategy is developed for early delivery of a reliable PDK with built-in statistical variability and reliability information. This enables TCAD-based transistor-SRAM co-design and path finding for emerging technology nodes.

Predictive Simulation and Benchmarking of Si and Ge pMOS FinFETs for Future CMOS Technology

In this paper, we study and compare Si versus Ge pMOS FinFETs at advanced node dimensions using ensemble Monte Carlo simulations. It is found that due to large external resistance, lack of stressing methods, smaller bandgap, larger dielectric constant, and increased variability that in the absence of major innovation, Ge is not an ideal candidate for channel replacement material of pMOS in future CMOS technology generation FinFETs. In order for Ge to compete with Si, it would at a minimum require a stressing mechanism and improved contact resistance, but leakage and variability would still be a concern for low-power applications.

Hierarchical Simulation of Statistical Variability: From 3-D MC With “ ab initio” Ionized Impurity Scattering to Statistical Compact Models

Quantum corrections based on density gradient formalism, recently introduced in the 3-D Monte Carlo (MC) module of the Glasgow “atomistic” simulator, are used to simultaneously capture quantum confinement effects as well as “ab initio” ionized impurity scattering. This has allowed us to consistently study the impact of transport variability due to scattering from random discrete dopants on the on-current variability in realistic nano-CMOS transistors. Such simulations result in an increased drain current variability when compared with the drift diffusion (DD) simulation. For the first time, a method that is used to accurately transfer the increased on-current variability obtained from the “ ab initio” MC simulations to the DD simulations is subsequently presented. The MC-corrected DD simulations are used to produce the target I-V characteristics from which the statistical compact models are extracted for use in preliminary design kits at the early stage of new technology development.

Simulation of “Ab Initio” Quantum Confinement Scattering in UTB MOSFETs Using Three-Dimensional Ensemble Monte Carlo

In this paper, we report a 3-D Monte Carlo (MC) simulation methodology that includes complex quantum confinement effects captured through the introduction of robust and efficient density gradient (DG) quantum corrections (QCs), which has been used to introduce “ab initio ” scattering from quantum confinement fluctuations in ultrathin body silicon-on-insulator metal-oxide-semiconductor field-effect transistors (MOSFETs) through the real space trajectories of the particles driven by the DG effective quantum potential and to study the enhanced current variability due to the corresponding transport variations. A “frozen field” approximation, where neither the field nor the QCs are updated, has been used to examine the dependence of mobility on silicon thickness in large self-averaging devices. This approximation, along with the MC simulations that are self-consistent with Poissons equation, is applied to study the variability of on-current due to random body thickness fluctuations in thin-body MOSFETs at low and high drain biases.