Campbell Millar

A Self-Consistent Full 3-D Real-Space NEGF Simulator for Studying Nonperturbative Effects in Nano-MOSFETs

In this paper, we present a full 3-D real-space quantum-transport simulator based on the Greens function formalism developed to study nonperturbative effects in ballistic nanotransistors. The nonequilibrium Green function (NEGF) equations in the effective mass approximation are discretized using the control-volume approach and solved self-consistently with the Poisson equation in order to obtain the electron and current densities. An efficient recursive algorithm is used in order to avoid the computation of the full Green function matrix. This algorithm, and the parallelization scheme used for the energy cycle, allow us to compute very efficiently the current-voltage characteristic without the simplifying assumptions often used in other quantum-transport simulations. We have applied our simulator to study the effect of surface roughness and stray charge on the ID-VG characteristic of a 6-nm Si-nanowire transistor. The results highlight the distinctly 3-D character of the electron transport, which cannot be accurately captured by using 1-D and 2-D NEGF simulations, or 3-D mode-space approximations.

Accurate Statistical Description of Random Dopant-Induced Threshold Voltage Variability

We have studied the detailed threshold voltage distribution in a state-of-the-art n-channel MOSFET in the presence of random discrete dopants. A ground-breaking sample of 100 000 transistors with statistically unique random dopant distributions were simulated using the Glasgow 3-D device simulator and advanced grid computing technologies. The results indicate that the threshold voltage distribution deviates substantially from a Gaussian distribution, which may have significant implications for the margins used in circuit design, particularly in SRAM cells.

Analysis of Threshold Voltage Distribution Due to Random Dopants: A 100 000-Sample 3-D Simulation Study

Using the Glasgow ldquoatomisticrdquo simulator, we have performed 3D statistical simulations of random-dopant-induced threshold voltage variation in state-of-the-art 35- and 13-nm bulk MOSFETs consisting of statistical samples of 105 or more microscopically different transistors. Simulation on such an unprecedented scale has been enabled by grid technology, which allows the distribution and the monitoring of very large ensembles on heterogeneous computational grids, as well as the automated handling of large amounts of output data. The results of these simulations show a pronounced asymmetry in the distribution of the MOSFET threshold voltages, which increases with transistor scaling. A comprehensive statistical analysis enabled by the large sample size reveals the origin of this observed asymmetry, provides a detailed insight into the underlying physical processes, and enables the statistical enhancement of simulations of random-dopant-induced threshold voltage variation.

Statistical-Variability Compact-Modeling Strategies for BSIM4 and PSP

The strategy to generate statistical model parameters is essential for variability-aware design. Based on 3D atomistic simulation results, this article evaluates the accuracy of statistical parameter generation for two industry-standard compact device models.

Interplay Between Process-Induced and Statistical Variability in 14-nm CMOS Technology Double-Gate SOI FinFETs

This paper presents a comprehensive simulation study of the interactions between long-range process and short-range statistical variability in a 14-nm technology node silicon-on-insulator FinFET. First, the individual and combined impact of the relevant variability sources, including random discrete dopants, fin line edge roughness (LER), gate LER, and metal gate granularity are studied for the nominal 20-nm physical gate-length FinFET design. This is followed by a comprehensive study of the interactions of the channel length, fin width and fin height systematic process variations with the combined statistical variability sources. The simulations follow a 3×3×3=27 experiment design that covers the process variability space, and 1000 statistical simulations are carried out at each node of the experiment. Both metal-gate-first and metal-gate-last technologies are considered. It is found that statistical variability is significantly dependent on the process-induced variability. The applicability of the Pelgrom law to the FinFET statistical variability, subject to long-range process variations, is also examined. Mismatch factor is strongly dependent on the process variations.

Understanding LER-Induced MOSFET

In this paper, using computationally intensive 3-D simulations in a grid computing environment, we perform a detailed study of line-edge-roughness (LER)-induced threshold voltage variability in contemporary MOSFETs. Statistical ensembles of tens of thousands transistors have been simulated. Our analysis has been predominantly performed on a 35-nm channel-length bulk MOSFET test bed, widely used in previous studies to investigate the impact of different statistical variability sources. Comprehensive data mining and statistical analysis provide information about the shape of the distribution of the device threshold voltage, which is significantly non-Gaussian. Strong nonlinear correlation has been observed between the threshold voltage and the average channel length of the simulated devices. The width dependence of LER-induced threshold voltage variability has also been simulated and analyzed. Additional confirmation of the basic conclusions from the simulation and statistical analysis of the 35-nm test bed transistor is provided by the simulation of a 42-nm physical channel-length bulk LP MOSFET, a 32-nm channel-length thin-body silicon-on-insulator (SOI) MOSFET, and a 22-nm channel-length double-gate (DG) MOSFET.

V_{T}

Increasing CMOS device variability has become one of the most acute problems facing the semiconductor manufacturing and design industries at, and beyond, the 45 nm technology generation. Most problematic of all is the statistical variability introduced by the discreteness of charge and granularity of matter in transistors with features already of molecular dimensions [i]. Two transistors next to each other on the chip with exactly the same geometries and strain distributions may have characteristics from each end of a wide statistical distribution. In conjunction with statistical variability [ii], negative bias temperature instability (NBTI) and/or hot carrier degradation can result in acute statistical reliability problems. It already profoundly affects SRAM design, and in logic circuits causes statistical timing problems and is increasingly leading to hard digital faults. In both cases, statistical variability restricts supply voltage scaling, adding to power dissipation problems [iii]. In this invited paper we describe recent advances in predictive physical simulation of statistical variability using drift diffusion (DD), Monte Carlo (MC) and quantum transport (QT) simulation techniques.

Variability—Part I: Three-Dimensional Simulation of Large Statistical Samples

In this paper, we use an automated tool flow in a 14 nm CMOS fin-shaped field-effect transistor (FinFET)/ static random access memory (SRAM) simulation-based design-technology cooptimization (DTCO) including both process-induced and intrinsic statistical variabilities. A 22 nm FinFET CMOS technology is used to illustrate the sensitivity to process-induced fin shape variation and to motivate this paper. Predictive Technology Computer Aided Design (TCAD) simulations have been carried out to evaluate the transistor performance ahead of silicon. Draft-diffusion simulations calibrated to the ensemble Monte Carlo simulation results are used to explore the process and the statistical variability space. This has been enabled by the automation of the tool flow and the dataset handling. The interplay between the process and the statistical variability has been examined in details. A two-stage compact model strategy is used to capture the interplay between process and statistical variability. To close the DTCO loop, the static noise margin and write noise margin sensitivity to cell design parameters and variability in FinFET-based SRAM designs are studied in details.

Advanced simulation of statistical variability and reliability in nano CMOS transistors

In this paper we summarize the impact of Statistical Variability (SV) on device performances and study the impact of oxide trapped charges in combination with SV. Traps time constants are described and analysed in combination with SV and time dependent simulations are performed including SV, random traps and charge injection stochasticity. Finally we demonstrate the necessity of statistical simulations in extracting compact models of aged devices and we address the problem of aged SRAM cell reliability.

Variability Aware Simulation Based Design- Technology Cooptimization (DTCO) Flow in 14 nm FinFET/SRAM Cooptimization

We study, in detail, statistical threshold voltage variability in a state of the art n-Channel MOSFET introduced by line edge roughness. A large sample of 35,000 transistors with microscopically different LER patterns was simulated using the Glasgow 3D ‘atomistic’ device simulator. Such large-scale simulation has been enabled by advanced grid computing technology. The results show that the statistical distribution of threshold voltage due to LER is asymmetric. Detailed analysis of the simulation results provide in depth understanding of the physical mechanisms governing LER induced statistical variability.