C. Andras Moritz

Heterogeneous Two-Level Logic and Its Density and Fault Tolerance Implications in Nanoscale Fabrics

Most proposed nanoscale computing architectures are based on a certain type of two-level logic family, e.g., AND-OR, NOR-NOR, NAND-NAND, etc. In this paper, a new fabric architecture that combines different logic families in the same nanofabric is proposed for higher density and better defect tolerance. To achieve this, we apply very minor modifications on the way of controlling nanogrids, while the basic manufacturing requirements remain the same. The fabric that is based on the new heterogeneous two-level logic yields higher density for the applications mapped to it. We find that it also improves the efficiency of fault tolerance techniques as it significantly simplifies the designs. In addition, we found that it enables voting at nanoscale that can improve fault tolerance further. A nanoscale processor is implemented for evaluation purposes. We found that compared with an implementation on a Nanoscale Application-Specific IC (NASIC) fabric with one type of two-level logic, the density of this processor improves by up to 52% by using the heterogeneous logic. Furthermore, the yield is improved by 15% at 2% defective transistors and by 147% at 5% defect rates. Detailed analysis on density and yield is provided. The approach is applicable in grid-based fabrics in general, e.g., it can be used in both NASIC and hybrid semiconductor/nanowire/molecular (CMOL) designs.

Spin wave functions nanofabric update

We provide a comprehensive progress update on the magnonic spin wave functions nanofabric. Spin wave propagation does not involve any physical movement of charge particles. Information is encoded in the phase of the wave and computation is based on the principle of superposition. This provides a fundamental advantage over conventional charge based electronics and opens new horizons for novel nano-scale architectures. The coupling mechanism between the spin and charge domain is enabled by the Magneto-Electric (ME) cells. Based on our experimental work we show that, an electric field of ∼1MV/m would be required to obtain 90 degree magnetization rotation. The paper also provides a methodology for estimating ME cell switching energy. In particular, we show that this energy can be as low as 10aJ. In addition, we discuss different topology options and circuit styles for 1-bit/2-bit magnonic adders. Our estimates on benefits vs. 45nm CMOS implementation show that, for a 1-bit adder, ∼40X reduction in area and ∼60X reduction in power is possible with the spin wave based implementation. For the 2-bit adder, results show that ∼33x area reduction and ∼40X reductions in power may be possible.

Towards logic functions as the device

This paper argues for alternate state variables and new types of sophisticated devices that implement more functionality in one computational step than typical devices based on simple switches. Elementary excitations in solids enabling wave interactions are possible initial candidates to create such new devices. The paper focuses on magnon-based spin-wave-logic functions (SPWF) and presents high fan-in majority, weighted high fan-in majority, and frequency-multiplexed weighted high fan-in majority devices as initial SPWFs. Experiments proving feasibility are also shown. Benefits vs. scaled CMOS are quantified. Results show that for 128 or larger inputs even a 2.5µm SPWF carry-look-ahead adder implementation is faster than the 45nm CMOS version. The 45nm SPWF adder is expected to be significantly faster across the whole range of input widths. In particular, the 45nm SPWF CLA adder is estimated to be at least 77X faster than CMOS version for input widths equal to or greater than 1024. A second example of a counter circuit is presented to illustrate the considerable reduction in complexity possible vs. CMOS.

Parameter Variability in Nanoscale Fabrics: Bottom-Up Integrated Exploration

Emerging nano-device based architectures will be impacted by parameter variation in conjunction with high defect rates. Variations in key physical parameters are caused by manufacturing imprecision as well as fundamental atomic scale randomness. In this paper, the impact of parameter variation on nanoscale computing fabrics is extensively studied through a novel integrated methodology across device, circuit and architectural levels. This integrated framework enables to study in detail the impact of physical parameter variation across all fabric layers for the first time. The framework, while generic, is explored extensively on the Nanoscale Application Specific Integrated Circuits (NASICs) nanowire fabric. For key physical parameters, the on current is found to vary by up to 3.5X. Circuit-level delay shows up to 40% deviation from nominal. Monte Carlo simulations using the architectural simulator found 67% nanoprocessor chips to operate below nominal frequencies due to variation. However, given high defect rates in nano-manufacturing, built-in fault tolerance needs to be incorporated for achieving acceptable yields. These techniques are shown to also ameliorate the effects of parameter variation.

Heterogeneous integration of epitaxial nanostructures - Strategies and application drivers

In order to sustain the historic progress in information processing, transmission, and storage, concurrent integration of heterogeneous functionality and materials with fine granularity is clearly imperative for the best connectivity, system performance, and density metrics. In this paper, we review recent developments in heterogeneous integration of epitaxial nanostructures for their applications toward our envisioned device-level heterogeneity using computing nanofabrics. We first identify the unmet need for heterogeneous integration in modern nanoelectronics and review state-of-the-art assembly approaches for nanoscale computing fabrics. We also discuss the novel circuit application driver, known as Nanoscale Application Specific Integrated Circuits (NASICs), which promises an overall performance-power-density advantage over CMOS and embeds built-in defect and parameter variation resilience. At the device-level, we propose an innovative cross-nanowire field-effect transistor (xnwFET) structure that simultaneously offers high performance, low parasitics, good electrostatic control, ease-of-manufacturability, and resilience to process variation. In addition, we specify technology requirements for heterogeneous integration and present two wafer-scale strategies. The first strategy is based on ex situ assembly and stamping transfer of pre-synthesized epitaxial nanostructures that allows tight control over key nanofabric parameters. The second strategy is based on lithographic definition of epitaxial nanostructures on native substrates followed by their stamping transfer using VLSI foundry processes. Finally, we demonstrate the successful concurrent heterogeneous co-integration of silicon and III-V compound semiconductor epitaxial nanowire arrays onto the same hosting substrate over large area, at multiple locations, with fine granularity, close proximity and high yield.

Variability in Nanoscale Fabrics: Bottom-up Integrated Analysis and Mitigation

Emerging nanodevice-based architectures will be impacted by parameter variation in conjunction with high defect rates. Variations in key physical parameters are caused by manufacturing imprecision as well as fundamental atomic scale randomness. In this article, the impact of parameter variation on nanoscale computing fabrics is extensively studied through a novel integrated methodology across device, circuit and architectural levels. This integrated approach enables to study in detail the impact of physical parameter variation across all fabric layers. A final contribution of the article includes novel techniques to address this impact. The variability framework, while generic, is explored extensively on the Nanoscale Application Specific Integrated Circuits (NASICs) nanowire fabric. For variation of σ = 10 in key physical parameters, the on current is found to vary by up to 3.5X. Circuit-level delay shows up to 118% deviation from nominal. Monte Carlo simulations using an architectural simulator found 67% nanoprocessor chips to operate below nominal frequencies due to variation. New built-in variation mitigation and fault-tolerance schemes, leveraging redundancy, asymmetric delay paths and biased voting schemes, were developed and evaluated to mitigate these effects. They are shown to improve performance by up to 7.5X on a nanoscale processor design with variation, and improve performance in designs relying on redundancy for defect tolerance, without variation assumed. Techniques show up to 3.8X improvement in effective-yield performance products even at a high 12% defect rate. The suite of techniques provides a design space across key system-level metrics such as performance, yield and area.

Incorporating Heterogeneous Redundancy in a Nanoprocessor for Improved Yield and Performance

Emerging nano-device based architectures are expected to experience high defect rates associated with the manufacturing process. In this paper, we introduce a novel built-in heterogeneous fault-tolerance scheme, which incorporates redundant circuitry into the design to provide fault tolerance. A thorough analysis of the new scheme was carried out for various system level metrics. The implementation and analysis were carried out on WISP-0, a stream processor implemented on the Nanoscale Application Specific Integrated Circuits (NASIC) fabric. We show that intelligent assignment of redundancy levels and nanoscale-voting strategies across WISP-0 greatly improves area, effective yield and performance for the nano-processor. The new scheme outperforms homogeneous schemes for a defect range of 3% to 9.75% where the metric used is the product of performance and effective yield.

A new tunnel-FET based RAM concept for ultra-low power applications

Maintaining power scaling trend and cell stability are critical challenges facing CMOS SRAM at sub-20nm technologies. These challenges primarily stem from the fundamental limitations of MOSFETs, and the rigid device doping and sizing requirements of underlying SRAM design. In this paper, we propose a new volatile memory architecture called Tunnel FET based Random Access Memory (TNRAM) that solves CMOS SRAM scaling challenges through integration of ultra-low power Tunnel FETs (TFETs) in a novel circuit style. It is designed to operate with single type uniform transistors to eliminate nanoscale device sizing requirements, and is customized to prevent SRAM like stability concerns. Analytical projections show significant power benefits; 6T-TNRAM has 4.38x lower active power and 174x lower leakage power over HP 6T-SRAM at 16nm technology node.

Parameter variation sensing and estimation in nanoscale fabrics

Abstract Parameter variations introduced by manufacturing imprecision are becoming more influential on circuit performance. This is especially the case in emerging nanoscale computing fabrics due to unconventional manufacturing steps and aggressive scaling. On-chip variation sensors are gaining in importance since post-fabrication compensation techniques can be employed. In estimation with on-chip variation sensors, however, random variations are masked because of well-known averaging effects during measurements. We propose a new on-chip sensor for nanoscale computing fabrics to estimate random variations in physical parameters. We show detailed estimation methodology and validate it with Monte Carlo simulations. The results show the sensor estimation error to be 8% on average and 12.7% in the worst case. In comparison to the well-known ring-oscillator based approach developed for CMOS, the estimation accuracy is 1.6 × better and requires 40 × less devices in on-chip sensors.

On-chip variation sensor for systematic variation estimation in nanoscale fabrics

Parameter variations caused by manufacturing imprecision at the nanoscale are expected to cause large deviations in electrical characteristics of emerging nanodevices and nano-fabrics leading to performance deterioration and yield loss. Parameter variation is typically addressed pre-fabrication, with circuit design targeting worst-case timing scenarios. By contrast, if variation is estimated post-manufacturing, adaptive techniques or reconfiguration could be used to provide more optimal level of tolerance. This paper presents a new on-chip sensor design for nanoscale fabrics that from its own variation, can estimate the extent of systematic variation in neighboring regions. A Monte Carlo simulation framework is used to validate the sensor design. Known variation cases are injected and based on sensor outputs, the extent of systematic variation in physical parameters is calculated. Our results show that the sensor has less than 1.2% error in estimation of physical parameters in 100% of injected variation cases. Based on published experimental data, the sensor estimation is shown to be accurate to within 2% of the actual physical parameter value for a range of up to 7mm.