Santosh Khasanvis

Self-Similar Magneto-Electric Nanocircuit Technology for Probabilistic Inference Engines

Probabilistic graphical models are powerful mathematical formalisms for machine learning and reasoning under uncertainty that are widely used for cognitive computing. However, they cannot be employed efficiently for large problems (with variables in the order of 100K or larger) on conventional systems, due to inefficiencies resulting from layers of abstraction and separation of logic and memory in CMOS implementations. In this paper, we present a magnetoelectric probabilistic technology framework for implementing probabilistic reasoning functions. The technology leverages straintronic magneto-tunneling junction (S-MTJ) devices in a novel mixed-signal circuit framework for direct computations on probabilities while enabling in-memory computations with persistence. Initial evaluations of the Bayesian likelihood estimation operation occurring during Bayesian Network inference indicate up to 127× lower area, 214× lower active power, and 70× lower latency compared to an equivalent 45-nm CMOS Boolean implementation.

Experimental prototyping of beyond-CMOS nanowire computing fabrics

Nanoscale 3D-integrated Application Specific ICs (N3ASICs) [1], a computing fabric based on semiconductor nanowire grids, is targeted as a scalable alternative to end-of-the-line CMOS. In contrast to device-centric approaches like CMOS, N3ASIC design choices across device, circuit and architecture levels are geared towards reducing manufacturing requirements while focusing on overall benefits. In this fabric, regular arrays with limited customization imply mitigated overlay precision requirements, novel circuit styles with single-type cross-nanowire FETs eliminate the need for arbitrary fine-grain sizing, doping and routing. In addition, junctionless transistors eliminate the need for stringent control of doping profiles. In this paper, we present theoretical and experimental progress towards realizing a functional N3ASIC prototype with junctionless transistors as active cross-point devices. We first validate this device concept through detailed 3D device simulations. We then present a manufacturing pathway as well as show experimental results demonstrating a proof-of-concept metal-gated junctionless nanowire device and N3ASIC tile structure with sub-30nm nanowires.

DESIGN OF SPIN WAVE FUNCTIONS-BASED LOGIC CIRCUITS

Over the past few years, several novel nanoscale computing concepts have been proposed as potential post-complementary metal oxide semiconductor (CMOS) computing fabrics. In these, key focus is on inventing a faster and lower power alternative to conventional metal oxide semiconductor field effect transators. Instead, we propose a fundamental shift in mindset towards more functional building blocks, replacing simple switches with more sophisticated information encoding and computing based on alternate state variables to achieve a significantly more efficient and compact logic. Specifically, we propose wave computation enabled by magnetic spin wave interactions called as spin wave functions (SPWFs). In SPWFs, computation is based on wave interference and information can be encoded in a waves phase, amplitude and frequency. In this paper, we provide an update on key fabric concepts and design aspects. Our analysis shows that circuit design choices can have a significant impact on overall fabric/device capabilities required and vice versa. Thereby, we adapt an integrated fabric-circuit exploration methodology. Control schemes for wave streaming and synchronization are also discussed with several SPWF circuit topologies. Our estimations show that significant area and power benefits can be expected for SPWF-based designs versus CMOS. In particular, for a 1-bit adder up to 40X area benefit and up to 304X power consumption reduction may be possible with SPWF-based implementation versus 45 nm CMOS.

Hybrid Graphene Nanoribbon-CMOS tunneling volatile memory fabric

Graphene exhibits extraordinary electrical properties and is therefore often envisioned to be the candidate material for post-silicon era as Silicon technology approaches fundamental scaling limits. Various Graphene based electronic devices and interconnects have been proposed in the past. In this paper, we explore the possibility of a hybrid fabric between CMOS and Graphene by implementing a novel Graphene Nanoribbon crossbar (xGNR) based volatile Tunneling RAM (GNT RAM) and integrating it with the 3D CMOS stack and layout. Detailed evaluation of GNT RAM circuits proposed show that they have considerable advantages in terms of power, area and write performance over 16nm CMOS SRAM. This work opens up other possibilities including multi-state memory fabrics and even an all-graphene fabric can be envisioned on the long term.

Architecting for Causal Intelligence at Nanoscale

Conventional Von Neumann microprocessors are inefficient for supporting machine intelligence due to layers of abstraction, limiting the feasibility of machine-learning frameworks in critical applications. A new approach for architecting intelligent systems, using physical equivalence and leveraging emerging nanotechnology, can pave the way to machine intelligence everywhere.

Spin wave nanofabric update

We provide a progress update on the spin wave nanofabric. The nanofabric comprises magneto-electric cells and spin wave buses serving for spin wave propagation. The magneto-electric cells are used as the input/output ports for information transfer between the charge and the spin domains, while information processing inside the nanofabric is via spin waves only. Information is encoded into the phase of the propagating spin wave, which makes it possible to utilize waveguides as passive logic elements and take the advantage of using wave superposition for data processing. This provides a fundamental advantage over the conventional transistor-based logic circuitry allowing for functional throughput enhancement and power consumption minimization at the same time. We present recent accomplishments in the magneto-electric element development and integration with spin wave buses. In particular, we show the excitation and detection of the spin waves via multiferroic elements. In addition, we present different approaches to magnonic logic circuit engineering and provide the comparison with CMOS by mapping the designs to 45nm NANGATE standard cell libraries. The estimates show more than 40X power reduction and 53X area reduction for magnonic circuits. These results illustrate the potential advantages over conventional charge based electronics that could be a route to beyond CMOS logic circuitry.

Manufacturing pathway and experimental demonstration for nanoscale fine-grained 3-D integrated circuit fabric

At Sub-20nm technologies CMOS scaling faces severe challenges primarily due to fundamental device scaling limitations, interconnection overhead and complex manufacturing. Migration to 3-D has been long sought as a possible pathway to continue scaling; however, CMOSs intrinsic requirements are not compatible for fine-grained 3-D integration. In [1], we proposed a truly fine-grained 3-D integrated circuit fabric called Skybridge that solves nanoscale challenges and achieves orders of magnitude benefits over CMOS. In Skybridge, device, circuit, connectivity, thermal management and manufacturing issues are addressed in an integrated 3-D compatible manner. At the core of Skybridges assembly are uniform vertical nanowires, which are functionalized with architected features for fabric integration. All active components are created primarily using sequential material deposition steps on these nanowires. Lithography and doping precision requirements are significantly reduced, and are primarily required in early stages. In this paper, we discuss manufacturing aspects of Skybridge fabric; we introduce Skybridges manufacturing pathway and show experimental demonstrations of key process steps.

Architecting connectivity for fine-grained 3-D vertically integrated circuits

Conventional CMOS technology is reaching fundamental scaling limits, and interconnection bottleneck is dominating IC power and performance. Migrating to 3-D integrated circuits, though promising, has eluded us due to inherent customization and manufacturing requirements in CMOS that are incompatible with 3-D organization. Skybridge, a fine-grained 3-D IC fabric technology was recently proposed towards this aim, which offers a paradigm shift in technology scaling and design. In this paper we present specifically architected core Skybridge structures to enable fine-grained connectivity in 3-D intrinsically. We develop predictive models for interconnect length distribution for Skybridge, and use them to quantify the benefits in terms of expected reduction in interconnect lengths and repeater counts when compared to 2-D CMOS in 16nm node. Our estimation indicates up to 10x reduction in longest global interconnect length vs. 16nm 2-D CMOS, and up to 2 orders of magnitude reduction in the number of repeaters for a design consisting of 10 million logic gates. These results show great promise in alleviating interconnect bottleneck due to a higher degree of connectivity in 3-D, leading to shorter global interconnects and reduced power and area overhead due to repeater insertion.

Architecting 3-D integrated circuit fabric with intrinsic thermal management features

Migration to 3-D provides a possible pathway for future Integrated Circuits (ICs) beyond 2-D CMOS, which is at the brink of its own fundamental limits. Partial attempts so far for 3-D integration using die to die and layer to layer stacking do not represent true progression, and suffer from their own challenges with lack of intrinsic thermal management being among the major ones. Our proposal for 3-D IC, Skybridge, is a truly fine-grained vertical nanowire based fabric that solves technology scaling challenges, and at the same time achieves orders of magnitude benefits over 2-D CMOS. Key to Skybridges 3-D integration is the fabric centric mindset, where device, circuit, connectivity, thermal management and manufacturing issues are co-addressed in a 3-D compatible manner. In this paper we present architected fine-grained 3-D thermal management features that are intrinsic components of the fabric and part of circuit design; a key difference with respect to die-die and layer-layer stacking approaches where thermal management considerations are coarse-grained at system level. Our bottom-up evaluation methodology, with simulations at both device and circuit level, shows that in the best case Skybridges thermal extraction features are very effective in thermal management, reducing temperature of a heated region by up to 92%.

Wave-based multi-valued computation framework

We present a novel multi-valued computation framework called Wave Interference Functions (WIF), based on emerging non-equilibrium wave phenomenon such as spin waves. WIF offers new features for data representation and computation, which can be game changing for post-CMOS integrated circuits (ICs). Information encoding wave attributes inherently leads to multi-dimensional multi-valued data representation and communication. Multi-valued computation is natively supported with wave interactions, such as wave superposition or interference. We introduce the concept of a multi-valued Interference Function that is more sophisticated than conventional Boolean and Majority functions, leading to compact circuits for logic. We present WIF implementation of multi-valued operators to realize any desired logic/arithmetic function using the Interference Function. We evaluate 2-digit to 16-digit quaternary (radix-4) full adder designs with WIF operators in terms of power, performance and area. Estimates indicate up to 63x higher density, 884x lower power and 3x better performance when compared to equivalent 45nm CMOS adders. WIF features completely change conventional assumptions on circuit design, opening new avenues to implement future nanoscale ICs for general purpose processing and other applications inherently suited to multi-valued computation.