Chi On Chui

On the Correct Extraction of Interface Trap Density of MOS Devices With High-Mobility Semiconductor Substrates

ldquoConventionalrdquo techniques and related capacitance-voltage characteristic interpretation were established to evaluate interface trap density on Si substrates. We show that blindly applying these techniques on alternative substrates can lead to incorrect conclusions. It is possible to both under- and overestimate the interface trap density by more than an order of magnitude. Pitfalls jeopardizing capacitance-and conductance-voltage characteristic interpretation for alternative semiconductor MOS are elaborated. We show how the conductance method, the most reliable and widely used interface trap density extraction method for Si, can be adapted and made reliable for alternative semiconductors while maintaining its simplicity.

Germanium MOS capacitors incorporating ultrathin high-/spl kappa/ gate dielectric

For the first time, we have successfully demonstrated the feasibility of integrating a high-permittivity (/spl kappa/) gate dielectric material zirconium oxide into the MOS capacitors fabricated on pure germanium substrates. The entire fabrication process was essentially performed at room temperature with the exception of a 410/spl deg/C forming gas anneal. After processing steps intended to remove the germanium native oxide interlayer between the zirconium oxide dielectric and germanium substrate, an excellent capacitance-based equivalent SiO/sub 2/ thickness (EOT) on the order of 5-8 /spl Aring/ and capacitance-voltage (C-V) characteristics with hysteresis of 16 mV have been achieved. Additionally, excellent device yield and uniformity were possible using this low thermal budget process.

Activation and diffusion studies of ion-implanted p and n dopants in germanium

We have demonstrated symmetrically high levels of electrical activation of both p- and n-type dopants in germanium. Rapid thermal annealing of various commonly implanted dopant species were performed in the temperature range of 600–850 °C in germanium substrates. Diffusion studies were also carried out by using different anneal times and temperatures. T-SUPREM™ simulations were used to fit the experimental profiles and to extract the diffusion coefficient of various dopants.

Germanium n-type shallow junction activation dependences

A few of the recent unsatisfactory germanium n-channel metal-oxide-semiconductor field-effect transistor MOSFET experimentations are believed to stem from the poor source and drain n+‐p junction formations. In order to explain the primary cause and suggest rectifying solutions, we have examined the activation of common n-type dopants in germanium and the related dependences. These dependences include thermal anneal budget, impurity species, and implantation dosage. Low thermal budgets are generally preferred to activate shallow junctions to simultaneously annihilate defects and suppress fast dopant diffusion. Injecting dopants over the solid-solubility limitation into shallow junctions would only generate more implantation damage but could not however lower the junction sheet resistance.

Atomic layer deposition of high-/spl kappa/ dielectric for germanium MOS applications - substrate

In this letter, we present the use of atomic layer deposition (ALD) for high-/spl kappa/ gate dielectric formation in Ge MOS devices. Different Ge surface cleaning methods prior to high-/spl kappa/ ALD have been evaluated together with the effects on inserting a Ge oxynitride (GeO/sub x/N/sub y/) interlayer between the high-/spl kappa/ layer and the Ge substrate. By incorporating a thin GeO/sub x/N/sub y/ interlayer, we have demonstrated excellent MOS capacitors with very small capacitance-voltage hysteresis and low gate leakage. Physical characterization has also been done to further investigate the quality of the oxynitride interlayer.

Effects of hydrogen annealing on heteroepitaxial-Ge layers on Si: Surface roughness and electrical quality

We have studied the effect of hydrogen annealing on the surface roughness of germanium (Ge) layers grown by chemical vapor deposition on silicon using atomic force microscopy and cross-sectional high resolution scanning electron microscopy (HR-SEM). Our results indicate a strong reduction of roughness that approaches 90% at 825°C. The smoother Ge surface allowed for the fabrication of metal-oxide-semiconductor capacitors using germanium oxynitride (GeOxNy) as the gate dielectric. Electrical quality was studied using high frequency capacitance–voltage characteristic of epi-Ge showing negligible hysteresis. We discuss the results in terms of Ge–H cluster formation, which lowers the diffusion barrier, allowing for higher diffusivity and surface mobility. The temperature dependence shows tapering off for temperatures exceeding 800°C, indicating a barrier reduction of ∼92meV.

Interfacial characteristics of HfO2 grown on nitrided Ge (100) substrates by atomic-layer deposition

The microstructural and electrical properties of Ge-based metal–oxide–semiconductor capacitors containing high-k gate dielectric layers were investigated with and without the presence of a GeOxNy interface layer. The effect of this nitrided layer on thermal stability of the metal oxide/Ge structures was probed by medium energy ion energy spectroscopy (MEIS). Atomic-layer deposited HfO2 on a chemical oxide-terminated Ge (100) surface exhibited poor capacitance–voltage behavior; however, direct substrate surface nitridation at 600°C in NH3 ambient before HfO2 deposition improved the carrier trapping characteristics. Diffusion of metal impurities (including Hf) into the interfacial oxide/Ge-substrate may be an important source of the measured degradation of electrical properties. MEIS results suggested that the GeOxNy interface layer may inhibit Hf diffusion into the underlying semiconductor at the temperatures investigated.

A sub-400/spl deg/C germanium MOSFET technology with high-/spl kappa/ dielectric and metal gate

A novel low thermal budget (/spl les/400/spl deg/C) germanium MOS process with high-/spl kappa/ gate dielectric and metal gate electrode has been demonstrated. For the first time, self-aligned surface-channel Ge p-MOSFETs with ZrO/sub 2/ gate dielectric having equivalent oxide thickness (EOT) of 6-10 /spl Aring/ and platinum gate electrode are demonstrated with twice the low-field hole mobility of Si MOSFETs.

Local epitaxial growth of ZrO2 on Ge (100) substrates by atomic layer epitaxy

High-k dielectric deposition processes for gate dielectric preparation on Si surfaces usually result in the unavoidable and uncontrolled formation of a thin interfacial oxide layer. Atomic layer deposition of ∼55-A ZrO2 film on a Ge (100) substrate using ZrCl4 and H2O at 300 °C was found to produce local epitaxial growth [(001) Ge//(001) ZrO2 and [100] Ge//[100] ZrO2] without a distinct interfacial layer, unlike the situation observed when ZrO2 is deposited using the same method on Si. Relatively large lattice mismatch (∼10%) between ZrO2 and Ge produced a high areal density of interfacial misfit dislocations. Large hysteresis (>200 mV) and high frequency dispersion were observed in capacitance–voltage measurements due to the high density of interface states. However, a low leakage current density, comparable to values obtained on Si substrates, was observed with the same capacitance density regardless of the high defect density.

Nanoscale germanium MOS Dielectrics-part I: germanium oxynitrides

In this paper, nanoscale germanium (Ge) oxynitride dielectrics are investigated for Ge MOS device applications. The synthesizing methodology and physical properties of these oxynitride films have been examined first. Basic electrical characteristics have been acquired on metal-gated MOS capacitors with Ge oxynitride dielectric on substrates with different dopant types and crystal orientations. Using an optimized oxidation and nitridation recipe, high-quality Ge MOS capacitors with a minimal frequency dispersion and capacitance-voltage hysteresis have been demonstrated. In addition, the Ge oxynitride dielectric-substrate interface has also been analyzed with the combined low-frequency-high-frequency capacitance method that revealed a substantial reduction of interface trap density after the forming gas anneal. An asymmetric interface trap density distribution within the Ge bandgap has been mapped out, which might explain the inferior n-channel Ge MOSFETs with oxynitride dielectric. An abnormality in the general gate leakage behavior has been observed and found to originate from a transient charge-trapping effect