C. Bermond

Integration and frequency dependent electrical modeling of Through Silicon Vias (TSV) for high density 3DICs

Evaluation of Through Silicon Via (TSV) electrical parameters is mandatory to improve heterogeneous 3D chip performance in the frame of a “more than Moore” roadmap. Accurate modeling of TSV is consequently essential to perform design, material and process optimizations. This paper presents a frequency dependent analytical model including MOS effect of high aspect ratio TSV achieved in a full CMOS 65 nm platform according to a face-to-face Via Last process. Specific test structures with bulk contacts to polarize silicon were integrated enabling C(V) and RF measurements. TSV equivalent model including all substrate effects is proposed and simplified according to CMOS 65 nm specificities (voltage, frequency, dimensions and Si conductivity) leading to a full analytical model.

Ferroelectric properties of Pb(Zr,Ti)O3 thin films until 40 GHz

The radio frequency characterization of Cu/TiN/Pb(Zr,Ti)O3 stack on glass is performed using coplanar transmission lines. A dielectric relaxation is evidenced around 10 GHz by the correlated decrease in the dielectric constant K together with the dielectric losses increase versus frequency. This phenomenon is attributed to domain wall relaxation. The ferroelectric nature of Pb(Zr,Ti)O3 (PZT) thin films is observed until 40 GHz with a hysteresis curve of K versus dc bias. The high K value (K∼1200) combined with a high tunability (∼35%) and moderate losses (∼1%) suggest that PZT films could be well suited for tunable devices for frequencies lower than 5 GHz.

Reliable 3D damascene MIM architecture embedded into Cu interconnect for a Ta 2 O 5 capacitor record density of 17 fF/μm 2

A new simple 3D Damascene architecture requiring only one additional mask is introduced for high-density MIM capacitors. TiN/Ta₂O₅/TiN stack deposited by PEALD has been integrated between Cu interconnect levels to maximize quality factor Q, reaching up to 17 fF/μm² capacitance. High-performance, breakdown voltages over 15 V and good linearity, C₁ = 76 ppm/V and C₂ = 63 ppm/V² at 100 kHz, make this capacitor an unique solution for analog and RF applications embedded in Cu BEOL.

Delay and Crosstalk on Future 32 nm Node Interconnects: Impact of ULK-Air-Gap Architecture

With technological developments towards 32 nm node ICs, interconnects effects have become fundamental on integrated circuits performances. Signal propagation will in particular be affected by complexity of technological stacks. In order to face integration and performance issues, air gap architecture constitutes a potential alternative to porous dielectric materials. After showing that air gap addresses the challenges on delay time for considered node, dimension effects corresponding to several kinds of applications will be analyzed in order to extract limits of integration regarding time-domain performances in terms of delay and crosstalk

Optimization of signal propagation performances in interconnects of the 45 nm node by exhaustive analysis of the technological parameters impact

Due to the continuous shrink of technology dimensions, parasitic propagation delay time and crosstalk at interconnect levels increasingly affect overall circuit performances. New materials, processes and architectures are now required to improve BEOL performances. A rigorous high-frequency electromagnetic approach including the scattering effects on Cu line resistance was developed for coupled narrow interconnects to analyze the actual benefits of these innovations for different signal types covering application range from logic to I/O. Effects of advanced metallization (ALD thin barriers), low-k insulators (porous ULKs, low-k barriers), and innovative architectures (hybrid stacks, air gaps, self-aligned barriers) on signal propagation performance were quantified, resulting in an effective process selection for the 45 nm technological node and below.

Performance predictions of prospective air gap architectures for the 22 nm node

With technological developments towards 22 nm node ICs, integration and process issues will be critical for signal propagation on interconnects. Air gap architecture, as a potential alternative to porous dielectrics, is thus analyzed for two SiO2 sacrificial approaches. Thanks to electromagnetic and time-domain simulations, extraction of barrier properties and dimensions limits regarding capacitance, delay and crosstalk parameters is realized, leading to the proposal of a specific stack as a global solution to this problematic.