C Brezina

Timepix3: a 65K channel hybrid pixel readout chip with simultaneous ToA/ToT and sparse readout

The Timepix3, hybrid pixel detector (HPD) readout chip, a successor to the Timepix \cite{timepix2007} chip, can record time-of-arrival (ToA) and time-over-threshold (ToT) simultaneously in each pixel. ToA information is recorded in a 14-bit register at 40 MHz and can be refined by a further 4 bits with a nominal resolution of 1.5625 ns (640 MHz). ToT is recorded in a 10-bit overflow controlled counter at 40 MHz. Pixels can be programmed to record 14 bits of integral ToT and 10 bits of event counting, both at 40 MHz. The chip is designed in 130 nm CMOS and contains 256 × 256 pixel channels (55 × 55 μm2). The chip, which has more than 170 M transistors, has been conceived as a general-purpose readout chip for HPDs used in a wide range of applications. Common requirements of these applications are operation without a trigger signal, and sparse readout where only pixels containing event information are read out. A new architecture has been designed for sparse readout and can achieve a throughput of up to 40 Mhits/s/cm2. The flexible architecture offers readout schemes ranging from serial (one link) readout (40 Mbps) to faster parallel (up to 8 links) readout of 5.12 Gbps. In the ToA/ToT operation mode, readout is simultaneous with data acquisition thus keeping pixels sensitive at all times. The pixel matrix is formed by super pixel (SP) structures of 2 × 4 pixels. This optimizes resources by sharing the pixel readout logic which transports data from SPs to End-of-Column (EoC) using a 2-phase handshake protocol. To reduce power consumption in applications with a low duty cycle, an on-chip power pulsing scheme has been implemented. The logic switches bias currents of the analog front-ends in a sequential manner, and all front-ends can be switched in 800 ns. The digital design uses a mixture of commercial and custom standard cell libraries and was verified using Open Verification Methodology (OVM) and commercial timing analysis tools. The analog front-end and a voltage-controlled oscillator for 1.5625 ns timing resolution have been designed using full custom techniques.

Architectural modeling of pixel readout chips Velopix and Timepix3

We examine two digital architectures for front end pixel readout chips, Velopix and Timepix3. These readout chips are developed for tracking detectors in future high energy physics experiments. They must incorporate local intelligence in pixels for time-over-threshold measurement and sparse readout. In addition, Velopix must be immune to single-event upsets in its digital logic. The most important requirements for both chips are pixel size, timing resolution, low power and high-speed sparse readout. We describe the transaction level architectural models of the chips using SystemVerilog. The correctness of the models is ensured using Open Verification Methodology. We will also discuss the advantages gained from transaction level modeling.

GOSSIPO-3: measurements on the prototype of a read-out pixel chip for Micro-Pattern Gaseous Detectors

GOSSIPO-3 is a demonstrator of a front-end chip designed in IBM 130 nm CMOS in collaboration between Nikhef (Amsterdam) and the Physics Department of the University of Bonn for the read-out of Micro-Pattern Gas Detectors. The prototype features charge sensitive amplifiers, discriminators, a high resolution Time to Digital Converter (TDC), two different Low Drop Out (LDO) voltage regulators for supply voltage control of the Time to Digital Converter, biasing circuits and control logic on a 2 × 1 mm2 die. The chip can be operated in a time measuring mode or an event counting mode. Following the prototype announcement at the TWEPP 2009, measurement data on gain, noise performance, channel to channel ToT spread and LDO load step responses is now available. The measurement results confirm the high gain and low noise (ENC = 25 e−) predicted by simulations. Stable and reproducible time bin sizes of the TDC are also confirmed.

A Time Projection Chamber with triple GEM and pixel readout

A Time Projection Chamber with a maximum drift distance of 26 cm was equipped with a triple GEM and a high resolution pixel readout. This detector was set up in a cosmic ray test-stand and 40 000 tracks have been recorded. It was shown, that the transverse spatial resolution in dependence on the drift distance was close to the diffusion limit of single electrons. In an electron test beam with an energy of 0.5 GeV it could be demonstrated that the data show no significant dependence on the track inclination within the pad plane.

Operation of a GEM-TPC with pixel readout

A prototype time projection chamber with 26 cm drift length was operated with a short-spaced triple gas electron multiplier (GEM) stack in a setup triggering on cosmic muon tracks. A small part of the anode plane is read out with a CMOS pixel application-specified integrated circuit (ASIC) named Timepix, which provides ultimate readout granularity. Pixel clusters of charge depositions corresponding to single primary electrons are observed and analyzed to reconstruct charged particle tracks. A dataset of several weeks of cosmic ray data is analyzed. The number of clusters per track length is well described by simulation. The obtained single point resolution approaches 50 μm at short drift distances and is well reproduced by a simple model of single-electron diffusion .

Time projection chamber with triple GEM and pixel readout

A Time Projection Chamber with a maximum drift distance of 26 cm was equipped with a triple GEM and a high resolution pixel readout. This detector was set up in a cosmic ray test-stand and 40 000 tracks have been recorded. It was shown, that the transverse spatial resolution in dependence on the drift distance was close to the diffusion limit of single electrons. In an electron test beam with an energy of 0.5 GeV it could be demonstrated that the data show no significant dependence on the track inclination within the pad plane.

GOSSIPO-4: Evaluation of a Novel PLL-Based TDC-Technique for the Readout of GridPix-Detectors

The direct readout of Micro-Pattern Gaseous Detectors (MPGDs) with bare pixel chips introduces the need for a new generation of readout electronics featuring a high spatial granularity as well as a highly accurate time measurement in each pixel. GOSSIPO-4, fabricated in a 130 nm CMOS technology, is a demonstrator ASIC investigating the potential of a new TDC-concept that is based on a chip-wide 40 MHz clock which is complemented by an additional 640 MHz clock. The latter is created upon demand by local oscillators distributed across the pixel matrix. PLL tuning of the local oscillators allows for automatic compensation of frequency fluctuations caused by process parameter, supply voltage and temperature variations. The developed PLL locks within 4 μs and achieves a duty cycle of 50.75% with a time interval error of only 23.4 ps. Mean DNL and INL of the TDC are less than 20% of the time bin size of 1.56 ns under all anticipated conditions.

Digital column readout architectures for hybrid pixel detector readout chips

In this paper, two digital column architectures suitable for sparse readout of data from a pixel matrix in trigger-less applications are presented. Each architecture reads out a pixel matrix of 256 x 256 pixels with a pixel pitch of 55 μm. The first architecture has been implemented in the Timepix3 chip, and this is presented together with initial measurements. Simulation results and measured data are compared. The second architecture has been designed for Velopix, a readout chip planned for the LHCb VELO upgrade. Unlike Timepix3, this has to be tolerant to radiation-induced single-event effects. Results from post-layout simulations are shown with the circuit architectures.

Gaseous detectors with micropattern gas amplification stages and CMOS pixel chip readout

Gas Electron Multipliers (GEMs) and Micromegas have demonstrated a very good performance in many applications. In particular, the spatial resolution has improved significantly compared to wire-based gaseous detectors. Because of the small pitch between the sensitive areas of gas amplification the limiting factor is usually given by the readout structure. To fully exploit the benefits of MPGDs we used a Timepix chip, a CMOS pixel chip with a pixel pitch of 55 μm, in combination with a GEM stack or a Micromegas realized as an InGrid structure. Both combinations have been tested in a time projection chamber (TPC) with a maximum drift distance of 26 cm. Additionally, various pad sizes have been studied with the GEM setup to investigate their influence on several key parameters. Also, first measurements of an InGrid based X-ray detector are described. In particular, measurements of background events were performed to evaluate a possible application of the detector in low rate dark matter searches.

The charge pump PLL clock generator designed for the 1.56 ns bin size time-to-digital converter pixel array of the Timepix3 readout ASIC

Timepix3 is a newly developed pixel readout chip which is expected to be operated in a wide range of gaseous and silicon detectors. It is made of 256 × 256 pixels organized in a square pixel-array with 55 μm pitch. Oscillators running at 640 MHz are distributed across the pixel-array and allow for a highly accurate measurement of the arrival time of a hit. This paper concentrates on a low-jitter phase locked loop (PLL) that is located in the chip periphery. This PLL provides a control voltage which regulates the actual frequency of the individual oscillators, allowing for compensation of process, voltage, and temperature variations.