T. Poikela

Timepix3: a 65K channel hybrid pixel readout chip with simultaneous ToA/ToT and sparse readout

The Timepix3, hybrid pixel detector (HPD) readout chip, a successor to the Timepix \cite{timepix2007} chip, can record time-of-arrival (ToA) and time-over-threshold (ToT) simultaneously in each pixel. ToA information is recorded in a 14-bit register at 40 MHz and can be refined by a further 4 bits with a nominal resolution of 1.5625 ns (640 MHz). ToT is recorded in a 10-bit overflow controlled counter at 40 MHz. Pixels can be programmed to record 14 bits of integral ToT and 10 bits of event counting, both at 40 MHz. The chip is designed in 130 nm CMOS and contains 256 × 256 pixel channels (55 × 55 μm2). The chip, which has more than 170 M transistors, has been conceived as a general-purpose readout chip for HPDs used in a wide range of applications. Common requirements of these applications are operation without a trigger signal, and sparse readout where only pixels containing event information are read out. A new architecture has been designed for sparse readout and can achieve a throughput of up to 40 Mhits/s/cm2. The flexible architecture offers readout schemes ranging from serial (one link) readout (40 Mbps) to faster parallel (up to 8 links) readout of 5.12 Gbps. In the ToA/ToT operation mode, readout is simultaneous with data acquisition thus keeping pixels sensitive at all times. The pixel matrix is formed by super pixel (SP) structures of 2 × 4 pixels. This optimizes resources by sharing the pixel readout logic which transports data from SPs to End-of-Column (EoC) using a 2-phase handshake protocol. To reduce power consumption in applications with a low duty cycle, an on-chip power pulsing scheme has been implemented. The logic switches bias currents of the analog front-ends in a sequential manner, and all front-ends can be switched in 800 ns. The digital design uses a mixture of commercial and custom standard cell libraries and was verified using Open Verification Methodology (OVM) and commercial timing analysis tools. The analog front-end and a voltage-controlled oscillator for 1.5625 ns timing resolution have been designed using full custom techniques.

Review of hybrid pixel detector readout ASICs for spectroscopic X-ray imaging

Semiconductor detector readout chips with pulse processing electronics have made possible spectroscopic X-ray imaging, bringing an improvement in the overall image quality and, in the case of medical imaging, a reduction in the X-ray dose delivered to the patient. In this contribution we review the state of the art in semiconductor-detector readout ASICs for spectroscopic X-ray imaging with emphasis on hybrid pixel detector technology. We discuss how some of the key challenges of the technology (such as dealing with high fluxes, maintaining spectral fidelity, power consumption density) are addressed by the various ASICs. In order to understand the fundamental limits of the technology, the physics of the interaction of radiation with the semiconductor detector and the process of signal induction in the input electrodes of the readout circuit are described. Simulations of the process of signal induction are presented that reveal the importance of making use of the small pixel effect to minimize the impact of the slow motion of holes and hole trapping in the induced signal in high-Z sensor materials. This can contribute to preserve fidelity in the measured spectrum with relatively short values of the shaper peaking time. Simulations also show, on the other hand, the distortion in the energy spectrum due to charge sharing and fluorescence photons when the pixel pitch is decreased. However, using recent measurements from the Medipix3 ASIC, we demonstrate that the spectroscopic information contained in the incoming photon beam can be recovered by the implementation in hardware of an algorithm whereby the signal from a single photon is reconstructed and allocated to the pixel with the largest deposition.

Charged particle tracking with the Timepix ASIC

A prototype particle tracking telescope was constructed using Timepix and Medipix ASIC hybrid pixel assemblies as the six sensing planes. Each telescope plane consisted of one 1.4 cm2 assembly, providing a 256 ×256 array of 55μm square pixels. The telescope achieved a pointing resolution of 2.4μm at the position of the device under test. During a beam test in 2009 the telescope was used to evaluate in detail the performance of two Timepix hybrid pixel assemblies; a standard planar 300μm thick sensor, and 285μm thick double sided 3D sensor. This paper describes a charge calibration study of the pixel devices, which allows the true charge to be extracted, and reports on measurements of the charge collection characteristics and Landau distributions. The planar sensor achieved a best resolution of 4.0±0.1μm for angled tracks, and resolutions of between 4.4 and 11μm for perpendicular tracks, depending on the applied bias voltage. The double sided 3D sensor, which has significantly less charge sharing, was found to have an optimal resolution of 9.0±0.1μm for angled tracks, and a resolution of 16.0±0.2μm for perpendicular tracks. Based on these studies it is concluded that the Timepix ASIC shows an excellent performance when used as a device for charged particle tracking.

The LHCb VELO upgrade

Abstract The LHCb experiment plans to have a fully upgraded detector and data acquisition system in order to take data with instantaneous luminosities up to 5 times greater than currently. For this reason the first tracking and vertexing detector, the VELO, will be completely redesigned to be able to cope with the much larger occupancies and data acquisition rates. Two main design alternatives, micro-strips or pixel detectors, are under consideration to build the upgraded detector. This paper describes the options presently under consideration, as well as a few highlights of the main aspects of the current R&D. Preliminary results using a pixel telescope are also presented.

A prototype hybrid pixel detector ASIC for the CLIC experiment

A prototype hybrid pixel detector ASIC specifically designed to the requirements of the vertex detector for CLIC is described and first electrical measurements are presented. The chip has been designed using a commercial 65 nm CMOS technology and comprises a matrix of 64 × 64 square pixels with 25 μm pitch. The main features include simultaneous 4-bit measurement of Time-over-Threshold (ToT) and Time-of-Arrival (ToA) with 10 ns accuracy, on-chip data compression and power pulsing capability.

VeloPix: the pixel ASIC for the LHCb upgrade

The LHCb Vertex Detector (VELO) will be upgraded in 2018 along with the other subsystems of LHCb in order to enable full readout at 40 MHz, with the data fed directly to the software triggering algorithms. The upgraded VELO is a lightweight hybrid pixel detector operating in vacuum in close proximity to the LHC beams. The readout will be provided by a dedicated front-end ASIC, dubbed VeloPix, matched to the LHCb readout requirements and the 55 × 55 μm VELO pixel dimensions. The chip is closely related to the Timepix3, from the Medipix family of ASICs. The principal challenge that the chip has to meet is a hit rate of up to 900 Mhits/s, resulting in a required output bandwidth of more than 16 Gbit/s. The occupancy across the chip is also very non-uniform, and the radiation levels reach an integrated 400 Mrad over the lifetime of the detector.VeloPix is a binary pixel readout chip with a data driven readout, designed in 130 nm CMOS technology. The pixels are combined into groups of 2 × 4 super pixels, enabling a shared logic and a reduction of bandwidth due to combined address and time stamp information. The pixel hits are combined with other simultaneous hits in the same super pixel, time stamped, and immediately driven off-chip. The analog front-end must be sufficiently fast to accurately time stamp the data, with a small enough dead time to minimize data loss in the most occupied regions of the chip. The data is driven off chip with a custom designed high speed serialiser. The current status of the ASIC design, the chip architecture and the simulations will be described.

Architectural modeling of pixel readout chips Velopix and Timepix3

We examine two digital architectures for front end pixel readout chips, Velopix and Timepix3. These readout chips are developed for tracking detectors in future high energy physics experiments. They must incorporate local intelligence in pixels for time-over-threshold measurement and sparse readout. In addition, Velopix must be immune to single-event upsets in its digital logic. The most important requirements for both chips are pixel size, timing resolution, low power and high-speed sparse readout. We describe the transaction level architectural models of the chips using SystemVerilog. The correctness of the models is ensured using Open Verification Methodology. We will also discuss the advantages gained from transaction level modeling.

Electrical measurements of a multi-mode hybrid pixel detector ASIC for radiation detection

We present the first electrical measurements of an application-specific integrated circuit (ASIC) to be used in a hybrid pixel detector intended for dosimetry and radiation detection. The dosimeter has three programmable modes of operation: photon counting mode, energy integration mode, and dosimetry mode. The ASIC comprises a matrix of 16 by 16 (256 total) square pixels of 220 μm pitch, providing 12.4 mm2 of segmented active area. Each pixel can be configured to operate in one of the three radiation measurement modes, with programmable-depth counters and shift registers to tailor the data word size and optimise the readout frame-rate in a given mode. The individual energies of impinging photons are determined through programmable analogue energy threshold discrimination, time over threshold measurement, or a combination thereof. Furthermore, the dosimetry mode contains 16 digital energy thresholds and automatically sorts data into 16 corresponding energy bin registers. The chips output is therefore pre-processed charge spectra of the radiation field. This paper discusses results from measurements taken using programmable test-pulses to inject controlled stimuli into the pixel circuits.

Towards a new generation of pixel detector readout chips

The Medipix3 Collaboration has broken new ground in spectroscopic X-ray imaging and in single particle detection and tracking. This paper will review briefly the performance and limitations of the present generation of pixel detector readout chips developed by the Collaboration. Through Silicon Via technology has the potential to provide a significant improvement in the tile-ability and more flexibility in the choice of readout architecture. This has been explored in the context of 3 projects with CEA-LETI using Medipix3 and Timepix3 wafers. The next generation of chips will aim to provide improved spectroscopic imaging performance at rates compatible with human CT. It will also aim to provide full spectroscopic images with unprecedented energy and spatial resolution. Some of the opportunities and challenges posed by moving to a more dense CMOS process will be discussed.

Design of the analog front-end for the Timepix3 and Smallpix hybrid pixel detectors in 130 nm CMOS technology

This paper describes a front-end for hybrid pixel readout chips, which was developed for the Timepix3 and Smallpix ASICs. The front-end contains a single-ended preamplifier with a structure for leakage current compensation which can handle both signal polarities, and a single-threshold discriminator with compensation for pixel-to-pixel mismatch. Preamplifier and discriminator are required to be fast, to allow a Time-Of-Arrival (TOA) measurement with a resolution of 1.56 ns. Time-Over-Threshold (TOT) is also measured; the monotonicity of TOT with respect to the input charge is greatly improved as compared to the previous Timepix chip. The analog area is only 55 μm × 13.5 μm. Timepix3 has already been fabricated and the first test results are also presented in this paper.