C. Bun Seng

Single and dual strained channel analysis of vertical strained — SiGe impact ionization MOSFET (VESIMOS)

Single Channel (SC) and Dual Channel (DC) Vertical Strained-SiGe Impact Ionization MOSFET (VESIMOS) has been successfully simulated and analyzed in this paper. Found out that SC VESIMOS operate in conventional MOSFET mode at V_DS = 1.75V, with 10% to 30% Ge mole fraction. However for Ge=50%, its operated in Impact Ionization (II) mode with fast switching speed of subthreshold value, S=9.8 mV/dec. A better performance in threshold voltage, V_TH, S value and I_ON/I_OFF ratio were found in DC VESIMOS as compared to SC VESIMOS. The V_TH=0.6V, S=10.98 mV/dec and I_ON/I_OFF = 1×10¹³ were measured in DC VESIMOS with Ge=30% that clarify the advantage of DC utilization on VESIMOS device. These improvements were mainly due to the enhancement of electron mobility from 600 m²/V-s (first channel) to 1400 m²/V-s (second channel). The electron mobility was increased due to the splitting of conduction band valley into six fold where the electron mass are reduced in out of plane direction and thus enhanced the mobility of electron.

Electromyogram (EMG) Signal Processing Analysis for Clinical Rehabilitation Application

Analysis of electromyogram (EMG) signal processing and its application to identify human muscle strength of rehabilitation purpose has been successfully carried out in this paper. Single channel EMG signal was obtained from human muscle using non-invasive electrodes and further process by signal acquisition circuit to get a suitable signal to be process. In the first part of signal acquisition, the amplification circuit for the small EMG signal has been design successfully. After amplification stage EMG signal was digitized through analogue and digital converter (ADC) then further process in microcontroller (ATmega328) for getting accurate EMG signal. Finally, the processed EMG signal was classified into 6 different levels in order to display the muscle strength level of the user. This EMG device can be used to help the weak person or an elderly to identity their strength level of muscle for clinical rehabilitation purpose.

Impact of strain and DP position on the performance of Vertical Strained-SiGe Impact Ionization MOSFET incorporating dielectric pocket (VESIMOS-DP)

The Vertical Strained Silicon Germanium (SiGe) Impact Ionization MOSFET with Dielectric Pocket (VESIMOS-DP) has been successfully developed and analyzed in this paper. The strain is induced in the structure by varying the mole fraction of Silicon Germanium layer as well as the channel thickness. Increase in mole fraction at the interface of channel region results in increase in strain in the channel. In order to maintain strain in the channel region, a relaxed Si1-xGex layer is required. S value for DP place at source side is higher (S=24.4 mV/decade) as compared at the drain side (S=18.9 mV/decade) intrinsic region. The impact ionization rate depends on the electric field at drain side intrinsic zone. The vicinity of DP near the drain region reduces charge sharing effects associated with the source and thus improves impact ionization rate. Due to the DP layer, improve stability of threshold voltage, VTH and subthreshold slope, S was found for VESIMOS-DP device of various size ranging from 20nm to 80nm which justified the vicinity of DP on improving the performance of the device.

Enhanced reliability of vertical strained impact ionization MOSFET incorporating dielectric pocket for ultra-sensitive biosensor applications

Fast switching with an enhanced reliability device structure of Vertical Strained Impact Ionization MOSFET incorporating Dielectric Pocket (VESIMOS-DP) has been successfully design, simulated and analyzed in this paper. Ultra-low power with low subthreshold swing (S) and high breakdown voltage are imperative for ultra-sensitive biosensors. Impact ionization MOSFET (IMOS) is predicted to be capable of S as low as 20 mV/dec, which is much lower than Conventional MOSFET (CMOS). There are significant drop in subthreshold slope (S) while threshold voltage is increase as the body doping concentration increases. S value for DP place at source side is higher (S 24.4 mV/decade) as compared at the drain side (S 18.9 mV/decade) intrinsic region. The vicinity of DP near the drain region reduces charge sharing effects associated with the source and thus improves impact ionization rate. The introduction of a Dielectric Pocket (DP) is believed to be able to minimize the PBT effect while improving the reliability of the device by attaining higher breakdown voltage. Consequently, with the reduced of alloy scattering, the electron mobility has been improved by 22%. In many aspects, it is revealed that the incorporation of DP enhanced the reliability of VESIMOS for future development of nanoelectronic devices.

Equivalent Circuit Model Analysis of Vertical Impact Ionization MOSFET (IMOS)

In this paper, an equivalent circuit model is proposed that describes the avalanche and snapback characteristics of Vertical Impact Ionization MOSFET (IMOS). The equivalent circuit model is constructed using MOS transistors that represent the avalanche characteristics. The main goal is to predict the vertical IMOS integrated circuits by using circuit simulations. The vertical IMOS is predicted to have a lower subthreshold slope and high ratio of current. Besides that, the equivalent circuit model is explained which is include the parasitic bipolar transistor with a generated-hole-dependent base resistance. The models for parasitic bipolar is combined with a PSPICE MOS transistor model and it is represented the gate bias dependence of snapback characteristic. The equivalent circuit parameters are extracted from the reference experimental values of previous research and modified to reproduce the measured avalanche and snapback characteristic of the vertical IMOS transistor. The results show that 90% of the analysis subthreshold slope value of circuit simulations similar to the reference experimental value. The ratio of the current also shows almost the same behavior. Therefore, the equivalent circuit model for vertical IMOS can be used in circuit simulations.

The vertical strained impact ionization MOSFET (VESIMOS) for ultra-sensitive biosensor application

This paper venture into prospective ideas of finding the best feasible candidates for future bio-based sensor by exploring an emerging device structure with elevated performance and reliable outcomes of vertical strained impact ionization MOSFET (VESIMOS) with dual strained SiGe and dielectric pocket (DP) technology. An overview of the simulated fabrication process and the performance of the three promising candidates for succession of the conventional vertical Impact Ionization MOSFET (IMOS): Single Channel vertical strained impact ionization MOSFET (SC-VESIMOS) [13], Dual Channel vertical strained impact ionization MOSFET (DC-VESIMOS) [14] and vertical strained impact ionization MOSFET incorporating Dielectric Pocket (VESIMOS-DP) is investigated using Silvaco package. These three devices offer possibilities to overcome physical limits occurring during the continuous shrinking process like the limitation of the subthreshold swing S to 60 mV/dec at room temperature or rising leakage currents due to tunneling. The performance of these novel devices can be extremely promising for applications where ultra-high sensitivity and fast response is desirable. An ultra-low power with low Subthreshold Swing and high breakdown voltage are imperative for ultra-sensitive biosensor. Eventually, these devices will prolong the increase density of transistor on a chip for future application of biosensor nanoelectronics.

Physics-based modelling of vertical strained impact ionization MOSFET (VESIMOS)

CMOS device scaling faces several fundamental limits as it scaled beyond the sub-30nm regime. Non-scalability of the subthreshold slope (S) and adverse short channel effects degrading the current drivability and electron mobility of a MOSFET. An innovative device structure with appropriate device physics understanding is vitally needed for scaling the silicon MOSFET into nanometer regime. Underlying this problem is the subthreshold slope concept, which is a measure of switching abruptness in transistor. S is fundamentally limited at 60mV/decade by the drift-diffusion based transport in current CMOS technology. Impact ionization MOSFET (IMOS) that works on the principle of avalanche breakdown mechanism has become promising candidate to overcome this S value constraint. In this paper, we report for the first time an analytical modelling of vertical strained Impact Ionization MOSFET (VESIMOS). We derive the equations and their range of validity and compare the characteristic with TCAD simulations to give truthful interpretation and profound effects in evaluating the device operation for circuit application.

Characterization of vertical strained SiGe impact ionization MOSFET for ultra-sensitive biosensor application

This paper venture into prospective ideas of finding viable solution of nanoelectronics device design by an assessment of incorporating vertical impact-ionization MOSFET (IMOS) with strained SiGe technology into a formation of an emerging device structure with elevated performance and reliable outcomes for future bio-based sensor application. Impact Ionization FET biosensors can be extremely promising for applications where ultra-high sensitivity and fast response is desirable. An ultra-low power with low Subthreshold Swing and high breakdown voltage are imperative for ultra-sensitive biosensor. Impact ionization MOSFET (IMOS) is expected to have a subthreshold swing (S) down to 20 mV/dec which is much lower compared to Conventional MOSFET (CMOS). This will eventually enhanced the switching behavior of the transistor and enhancing its electrical performance and response time particularly when scaled down into nanometre regime. However, vertical IMOS experience parasitic bipolar transistors (PBT) effect and low breakdown voltage. Parasitic Bipolar Transistor effect is a phenomenon where the MOSFET act as a minority carrier device like BJT instead of majority carrier device. This is not favorable for any power device or sensor. Dielectric Pocket (DP) is believed to be able to minimize the PBT effect while improving the performance of the device. Eventually, this device will prolong the increase density of transistor in a chip for future application of biosensor nanoelectronics.

Body doping analysis of vertical strained-SiGe Impact Ionization MOSFET incorporating dielectric pocket (VESIMOS-DP)

The Vertical Strained Silicon Germanium (SiGe) Impact Ionization MOSFET with Dielectric Pocket (VESIMOS-DP) has been successfully developed and analyzed in this paper. There are significant drop in subthreshold slope (S) while threshold voltage is increase as the body doping concentration increases. It is notable that for body doping concentration above 1020, the S values keep increasing which is not recommended as the switching speed getting higher distracting performance of the device. An improved stability of threshold voltage, VTH was found for VESIMOS-DP device of various DP size ranging from 20nm to 80nm. The stability is due to the reducing charge sharing effects between source and drain region. In addition, the output characteristic was also highlighted a very good drain current at different gate voltage with the increasing of drain voltage for VESIMOS-DP with high body doping concentration. VESIMOS-DP with low body doping concentration suffers PBT effect that prevents the device from being able to switch off. Hence, high body doping concentrations are imperative for obtaining better device characteristics and ensure the device works in II mode.

Mobility enhancement on Vertical Strained-SiGe Impact Ionization MOSFET incorporating Dielectric Pocket (VESIMOS-DP)

The Vertical Strained Silicon Germanium (SiGe) Impact Ionization MOSFET with Dielectric Pocket (VESIMOS-DP) has been successfully developed and analyzed in this paper. The electron mobility in the VESIMOS-DP (~1440m2/V-s), was found to be increased by 4% in comparison to VESIMOS (~1386 m2/V-s) device. The mobilities in strained layer is depends on the transport direction, either parallel to the original SiGe growth interface or in the perpendicular direction. Carrier mobilities in strained SiGe layer is also based on the local distortion due to the strain effects which contribute to the alloy scattering on the carriers. With the vicinity of DP, the carrier scattering effect has reduced which merits the introduction of DP on the device. Due to the DP layer, improve stability of threshold voltage, VTH and subthreshold slope, S was found for VESIMOS-DP device of various size ranging from 20nm to 80nm justified the vicinity of the DP on improving the performance of the device.