Ismail Saad

Ballistic quantum transport in a nanoscale metal-oxide-semiconductor field effect transistor

The ballistic saturation velocity in a nanoscale metal-oxide-semiconductor field effect transistor (MOSFET) is revealed to be limited to the Fermi velocity in a degenerately induced channel appropriate for the quasi-two-dimensional nature of the inverted channel. The saturation point drain velocity is shown to rise with the increasing drain voltage approaching the intrinsic Fermi velocity, giving the equivalent of channel-length modulation. Quantum confinement effect degrades the channel mobility to the confining gate electric field as well as increases the effective thickness of the gate oxide. When the theory developed is applied to an 80nm MOSFET, excellent agreement to the experimental data is obtained.

The drain velocity overshoot in an 80 nm metal-oxide-semiconductor field-effect transistor

The current at the onset of saturation in a metal-oxide-semiconductor field-effect transistor (MOSFET) is shown to be limited by the drain velocity that increases toward its saturation value with the increase in the drain voltage. The saturation of velocity crops up as randomly oriented velocity vectors in equilibrium realign themselves to become unidirectional in the presence of an extremely high electric field. The intrinsic velocity, the ultimate saturation velocity, is the function of carrier concentration and temperature, consistent with the predictions of the ballistic transport. The presence of a quantum emission either by emission of a phonon or photon lowers the saturation velocity below its intrinsic value. Channel conduction beyond the quasisaturation point enhances due to the drain velocity overshoot as a result of enhanced drain electric field as drain voltage is increased. The excellent agreement with experimental data on an 80 nm channel, without using any artificial parameters, confirms th...

Ballistic mobility and saturation velocity in low-dimensional nanostructures

Ohms law, a linear drift velocity response to the applied electric field, has been and continues to be the basis for characterizing, evaluating performance, and designing integrated circuits, but is shown not to hold its supremacy as channel lengths are being scaled down. In the high electric field, the collision-free ballistic transport is predicted, while in low electric field the transport remains predominantly scattering-limited in a long-channel. In a micro/nano-circuit, even a low logic voltage of 1V gives an electric field that is above its critical value ec (e>>ec) triggering non-ohmic behavior that results in ballistic velocity saturation. The saturation velocity is an appropriate thermal velocity for a non-degenerate and Fermi velocity for a degenerate system with given dimensionality. A quantum emission may lower this ballistic velocity. The collision-free ballistic mobility in the ohmic domain arises when the channel length is smaller than the mean free path. The results presented will have a profound influence in interpreting the data on a variety of low-dimensional nanostructures.

Scattering-limited and ballistic transport in a nano-CMOS circuit

The mobility and saturation velocity in the nanoscale metal oxide semiconductor field effect transistor (MOSFET) are revealed to be ballistic; the former in a channel whose length is smaller than the scattering-limited mean free path. The drain-end carrier velocity is smaller than the ultimate saturation velocity due to the presence of a finite electric field at the drain. The current-voltage characteristics of a MOSFET are obtained and shown to agree well with the experimental observations on an 80nm channel. When scaling complementary pair of NMOS and PMOS channels, it is shown that the length of the channel is proportional to the channel mobility. On the other hand, the width of the channel is scaled inversely proportional to the saturation velocity of the channel. The results reported may transform the way the ULSI circuits are designed and their performance evaluated.

Vertical double gate MOSFET for nanoscale device with fully depleted feature

A fully depleted vertical double gate MOSFET device was revealed with the implementation of oblique rotating implantation (ORI) method in 25 nm silicon pillar thickness. Several devices with various gate lengths (20–100 nm) were simulated and evaluated using virtual wafer tool. The implication of gate length reduction on the short channel effect (SCE) shows considerable advantages with higher current drives at lower gate length, while the low subthreshold swing could balance the threshold voltage roll‐off in the term of increasing power consumption. As a result, the drive current and also SCE controllability will be a benefit in the fully depleted device.

Ballistic saturation velocity of quasi-2D Low- dimensional nanoscale field effect transistor (FET)

The saturation velocity is found to be ballistic regardless of the device dimensions. The ballistic intrinsic velocity is based on streamlining of the randomly oriented velocity vectors in zero electric field. In the degenerate realm, the saturation velocity is shown to be the Fermi velocity that is independent of temperature but strongly dependent on carrier concentration. In the non‐degenerate realm, it’s becomes thermal velocity that depends only on the ambient temperature. The drain carrier velocity is revealed to be smaller than the saturation velocity due to finite electric field at the drain‐end. An excellent agreement is revealed when comparing the model to 80 nm fabricated MOSFET.

Design and Simulation of 50 nm Vertical Double-Gate MOSFET (VDGM)

The paper demonstrate the design and simulation study of 2D vertical double- gate MOSFET (VDGM) with an excellent short channel effect (SCE) characteristics. With the gate length of 50 nm, body doping of 3.5 times 1018 cm-3 and oxide thickness, TOX = 2.5 nm, a good drive current ION of 7 muA/mum and a low off-state leakage current IOFF of 2 pA/mum was explicitly shown. Besides that, the subthreshold characteristics also highlighted a reasonably well-controlled SCE with subthreshold swing SubVT = 89 mV/decade and threshold voltage VT = 0.56 V. The analysis of body doping effects for SCE optimization and drive current trade-off was also done for an overall investigation and limit of the VDGM.

Numerical study of fermi energy for p-type silicon nanowire

There is huge interest in the development of one dimensional silicon nanowire with extremely narrow cylindrical channel body as these devices are promising to take CMOS to the end‐of‐the‐roadmap. The band structure of Silicon is parabolic, in this condition density of state proportion of Fermi‐Dirac integral that covers the carrier statistics to all degeneracy level is presented and its limits are obtained. In the nondegenerate regime the results replicate what is expected form, the Boltzmann statistics. However, the results vary in degenerate regime. Fermi energy with respect to band edge is function of temperature that independent of the carrier concentration in the nondegenrate regime. In the other strongly degenerate, the Fermi energy is a function of carrier concentration appropriate for given dimensionality, but is independent of temperature.

Analytical Study of Carrier Statistic in 2‐Dimensional Nanoscale P‐MOS

The carrier statistics for 2‐dimensional (2‐D) p‐type nanostructure was elaborated, especially for p‐MOSFET. According to the energy band diagram, the effective mass (m*) in the p‐type silicon is mostly dominated by heavy hole because of the large gap between heavy hole and light hole in k = 0. The carrier concentration in 2‐D was obtained using the calculated density of state, based on the Fermi—Dirac statistic on the order of zero (I0). In the nondegenerate regime the carrier statistic results replicate the form the Boltzmann statistics. However, the results vary in degenerate regime, which result in the presence of ηV. The results for 2‐D carrier statistic were numerically computed, and the comparison of the carrier statistic for degenerate and non‐degenerate regime is presented, along with its respective Fermi‐Dirac integral. It is also found that the density of state of hole in 2‐D p‐MOSFET is independent of the temperature.

Design and analysis of nanoscale vertical MOSFET using oblique rotating implantation (ORI) method with reduced parasitic capacitance

The design and analysis of an enhanced performance of vertical MOSFET is revealed by adopting the oblique rotating ion implantation (ORI) method combined with fillet oxidation (FILOX) technology. These CMOS compatible processes have formed the symmetrical self‐aligned source/drain regions over the silicon pillar with sharp vertical channel profiles. Accordingly, an increased numbers of electrons in the channel with decreased channel length (Lg) have shown to improved the threshold voltage, sub‐threshold swing, drive‐on current, leakage current, DIBL and drain saturation current significantly. The drain overlap capacitance is a factor of 0.2 lower and the source overlap capacitance is a factor of 1.5 lower than standard vertical MOSFETs.