C. Gerardi

Performance and reliability features of advanced nonvolatile memories based on discrete traps (silicon nanocrystals, SONOS)

In this paper, an overview of todays status and progress, as well as tomorrows challenges and trends, in the field of advanced nonvolatile memories based on discrete traps is given. In particular, unique features of silicon nanocrystal and SONOS memories will be illustrated through original recent data. The main potentials and main issues of these technologies as candidates to push further the scaling limits of conventional floating-gate Flash devices will be evaluated.

How far will silicon nanocrystals push the scaling limits of NVMs technologies

For the first time, memory devices with optimized high density (2E12#/cm/sup 2/) LPCVD Si nanocrystals have been reproducibly achieved and studied on an extensive statistical basis (from single cell up to 1 Mb test-array) under different programming conditions. An original experimental and theoretical analysis of the threshold voltage shift distribution shows that Si nanocrystals have serious potential to push the scaling of NOR and NAND flash at least to the 35 nm and 65 nm nodes, respectively.

Degradation and hard breakdown transient of thin gate oxides in metal–SiO2–Si capacitors: Dependence on oxide thickness

We have investigated the dynamics of hard intrinsic dielectric breakdown of gate oxide layers with thickness between 35 and 5.6 nm in n+ polycrystalline Si–SiO2–Si metal/oxide/semiconductor capacitors after constant voltage Fowler–Nordheim stress. The buildup of defects in the oxide during the degradation phase was monitored by quasi static C–V measurements. The dynamics of the final breakdown event was followed with high time resolution, allowing to measure voltage, current, and power versus time during the breakdown transient. Transmission electron microscopy data quantifying the damage produced during this transient are reported. Finally, we propose a phenomenological model concerning the dynamics of breakdown with model parameters adjusted on the basis of the experimental data.

Nanocrystal metal-oxide-semiconductor memories obtained by chemical vapor deposition of Si nanocrystals

We have realized nanocrystal memories by using silicon quantum dots embedded in silicon dioxide. The Si dots with the size of few nanometers have been obtained by chemical vapor deposition on very thin tunnel oxides and subsequently coated with a deposited SiO2 control dielectric. A range of temperatures in which we can adequately control a nucleation process, that gives rise to nanocrystal densities of ∼3×1011 cm−2 with good uniformity on the wafer, has been defined. The memory effects are observed in metal-oxide-semiconductor capacitors or field effect transistors by significant and reversible flat band or threshold voltage shifts between written and erased states that can be achieved by applying gate voltages as low as 5 V. The program-erase window does not exhibit any change after 105 cycles on large area cells showing that the endurance of such a memory device which uses a thinner tunnel oxide is potentially much higher than that of standard nonvolatile memories. Moreover, good retention results are ...

Nucleation kinetics of Si quantum dots on SiO2

The formation of Si quantum dots on SiO2 by chemical vapor deposition of SiH4 has been investigated in the range from the submonolayer to the complete coverage with Si. In order to investigate the very early stages of the nucleation process of Si on SiO2, the energy filtered transmission electron microscopy has been chosen as the main characterization technique, because of the high spatial resolution typical of the transmission electron microscopy analysis, coupled to the compositional information obtained by the electron energy loss spectroscopy. The plan view configuration has been used to measure the dot size distributions down to dimensions of about 1 nm, and in cross section to evaluate the dot wetting angle. For all the several experimental conditions, a wetting angle distribution has been obtained and has shown to be centered at about 90°. Data on the dot size distributions are shown and discussed in the framework of a continuous nucleation model, which has been implemented to take into account the...

Room-temperature single-electron effects in silicon nanocrystal memories

In this work, we present an experimental study on the single-electron effects observed at room temperature in silicon nanocrystal memories. The electrical characterization has been performed by means of a purposely designed low noise high bandwidth measurement system. Relevant statistical properties of the threshold voltage shifts induced by single-electron trapping and detrapping in the silicon dots are reported. The kinetics of electron capture and emission is also discussed.

Program/erase dynamics and channel conduction in nanocrystal memories

We present new models for nanocrystal (NC) memories, addressing program/erase (P/E) transients and carrier conduction in the channel controlled by discrete nodes. The model allows for the calculation of the achievable threshold-voltage (V/sub T/) window and P/E times under uniform tunneling-injection conditions. Comparisons with experimental data are shown, demonstrating that our physically-based model correctly captures the VT dependence on critical cell and bias parameters. The model can be used to draw technological guidelines for window optimization in NC cells.

Residual Crystalline Silicon Phase in Silicon-Rich-Oxide Films Subjected to High Temperature Annealing

Structural properties of silicon rich oxide films (SRO) have been investigated by means of micro-Raman spectroscopy and transmission electron microscopy (TEM). The layers were deposited by plasma enhanced chemical vapor deposition using different SiH 4 /O 2 gas mixtures. The Raman spectra of the as-deposited SRO films are dominated by a broad band in the region 400-500 cm -1 typical of a highly disordered silicon network. After annealing at temperatures above 1000°C in N 2 , the formation of silicon nanocrystals is observed both in the Raman spectra and in the TEM images. However, most of the precipitated silicon does not crystallize and assumes an amorphous microstructure.

Soft breakdown of gate oxides in metal–SiO2–Si capacitors under stress with hot electrons

We have investigated the intrinsic dielectric breakdown of gate oxide layers with thickness of 12 and 7 nm in n+ polycrystalline Si–SiO2–Si metal/oxide/semiconductor (MOS) capacitors after stress with constant current either under Fowler-Nordheim or under hot electron injection. Occurrence of soft breakdown without thermal damage in the MOS structure is demonstrated even in a 12 nm oxide under particular stress conditions. In general, it is found that the type of stress determines the breakdown mode (soft or hard).

A new channel percolation model for V/sub T/ shift in discrete-trap memories

In this work we studied the mechanisms for channel conduction in discrete-trap memories (DTMs). It is shown that the threshold voltage V/sub T/ in the cell corresponds to a percolation condition in the channel, where the inverted layers connect source to drain. A numerical model is presented which is able to calculate the local profile of V/sub T/ in the channel, and to evaluate the global V/sub T/ in the cell according to a channel percolation condition. The model is shown to account for the size dependence of V/sub T/ in DTM cells, and for the staircase charge-loss characteristics observed on ultrascaled devices. The implications of the percolation mechanism from the reliability point of view are finally discussed in details.