Massimo Melanotte

How far will silicon nanocrystals push the scaling limits of NVMs technologies

For the first time, memory devices with optimized high density (2E12#/cm/sup 2/) LPCVD Si nanocrystals have been reproducibly achieved and studied on an extensive statistical basis (from single cell up to 1 Mb test-array) under different programming conditions. An original experimental and theoretical analysis of the threshold voltage shift distribution shows that Si nanocrystals have serious potential to push the scaling of NOR and NAND flash at least to the 35 nm and 65 nm nodes, respectively.

Peculiar aspects of nanocrystal memory cells: data and extrapolations

Nanocrystal memory cell are a promising candidate for the scaling of nonvolatile memories in which the conventional floating gate is replaced by an array of nanocrystals. The aim of this paper is to present the results of a thorough investigation of the possibilities and the limitations of such new memory cell. In particular, we focus on devices characterized by a very thin tunnel oxide layer and by silicon nanocrystals formed by chemical vapor deposition. The direct tunneling of the electrons through the tunnel oxide, their storage into the silicon nanocrystals, and furthermore, retention, endurance, and drain turn-on effects, well-known issues for nonvolatile memories, are all investigated. The cell can be also programmed by channel hot electron injection, allowing the possibility to multibit storage. The suppression of the drain turn-on and the possibility of using this cell for multibit storage give us a clear evidence of the distributed nature of the charge storage.

Advantages of the FinFET architecture in SONOS and Nanocrystal memory devices

Double-gate and tri-gate FinFET type memories with nitride (SONOS-like) or Si nanocrystals storage with minimum feature sizes of 10 nm were realized. Strong performance advantages in program / erase characteristics and reliability deeply linked to the FinFET architecture are demonstrated.

Memory effects in MOS devices based on Si quantum dots

Abstract Silicon quantum dots have been deposited on top of a 3-nm tunnel oxide by Low Pressure Chemical Vapour Deposition (LPCVD) and coated with a 7-nm Chemical Vapour Deposited (CVD) oxide. This stack was then incorporated in Metal-Oxide-Semiconductor structure and used as floating gate of a memory cell. The presence of 3 nm of tunnel oxides allows the injection of the charge by direct tunnel (DT) using low voltages for both program and erase operations. The charge stored in the quantum dots is able to produce a well-detectable flat band shift in the capacitors or, equivalently, a threshold voltage shift in the transistors. Furthermore, due to the presence of SiO2 between the grains, the lateral charge loss is reduced and, thus, long retention time are possible. In this work we present good memory action characterised by low write voltages, write times of the order of milliseconds and long retention time in spite of the low tunnel oxide thickness.

Reliability and Retention Study of Nanocrystal Cell Array

We have studied nanocrystal memory arrays with 2.56 × 10 cells (256kb) in which Si nanocrystals have been obtained by CVD deposition on a 4nm tunnel oxide. The cells in the array are programmed and erased by electron tunneling through the SiO2 dielectric. We find that the threshold voltage distribution has little spread. In addition the arrays are also very robust with respect to drain stress and show good retention.

Location of holes in silicon-rich oxide as memory states

The induced changes of the flatband voltage by the location of holes in a silicon-rich oxide (SRO) film sandwiched between two thin SiO2 layers [used as gate dielectric in a metal–oxide–semiconductor (MOS) capacitor] can be used as the two states of a memory cell. The principle of operation is based on holes permanently trapped in the SRO layer and reversibly moved up and down, close to the metal and the semiconductor, in order to obtain the two logic states of the memory. The concept has been verified by suitable experiments on MOS structures. The device exhibits an excellent endurance behavior and, due to the low mobility of the holes at low field in the SRO layer, a much longer refresh time compared to conventional dynamic random access memory cells.

Highly manufacturable/low aspect ratio Si Nano Floating Gate FinFET memories: high speed performances and improved reliability

In this work we have studied sub-50 nm finFET nano-floating gate (NFG) Flash (FINFLASH) memory cells. Si nanocrystals have been used as NFG storage medium. Very low aspect ratio FINFLASH cells with fin height down to 20 nm have been investigated.

Non Volatile Memories-Status and Emerging Trends

Actual scenario and new trends in non volatile memories are presented, considering market, applications, scaling requirements, reliability and manufacturability constrains. EPROM and Flash-EEPROM are particularly reviewed, as the devices better representing speed and density progress, the two leading aspects along non volatile memories (NVM) evolution.

Memory effects in MOS capacitors with silicon quantum dots

Abstract To form crystalline Si dots embedded in SiO 2 , we have deposited thin films of silicon-rich oxide (SRO) by plasma-enhanced chemical vapor deposition of SiH 4 and O 2 . Then the materials have been annealed in N 2 ambient at temperatures between 950°C and 1100°C. Under such processing, the supersaturation of Si in the amorphous SRO film produces the formation of crystalline Si dots embedded in SiO 2 . The narrow dot size distributions, analyzed by transmission electron microscopy, are characterized by average grain radii and standard deviations down to about 1 nm. The memory function of such structures has been investigated in MOS capacitors with a SRO film sandwiched between two thin SiO 2 layers as insulator and with an n + polycrystalline silicon gate. The operations of write and storage are clearly detected by measurements of hysteresis in capacitance–voltage characteristics. A model which explains both the occurrence of steady-state conduction through the SiO 2 /SRO/SiO 2 stack at a relatively low voltage and the shift of flat-band voltage is presented and discussed.