G. Ammendola

Performance and reliability features of advanced nonvolatile memories based on discrete traps (silicon nanocrystals, SONOS)

In this paper, an overview of todays status and progress, as well as tomorrows challenges and trends, in the field of advanced nonvolatile memories based on discrete traps is given. In particular, unique features of silicon nanocrystal and SONOS memories will be illustrated through original recent data. The main potentials and main issues of these technologies as candidates to push further the scaling limits of conventional floating-gate Flash devices will be evaluated.

How far will silicon nanocrystals push the scaling limits of NVMs technologies

For the first time, memory devices with optimized high density (2E12#/cm/sup 2/) LPCVD Si nanocrystals have been reproducibly achieved and studied on an extensive statistical basis (from single cell up to 1 Mb test-array) under different programming conditions. An original experimental and theoretical analysis of the threshold voltage shift distribution shows that Si nanocrystals have serious potential to push the scaling of NOR and NAND flash at least to the 35 nm and 65 nm nodes, respectively.

Nanocrystal metal-oxide-semiconductor memories obtained by chemical vapor deposition of Si nanocrystals

We have realized nanocrystal memories by using silicon quantum dots embedded in silicon dioxide. The Si dots with the size of few nanometers have been obtained by chemical vapor deposition on very thin tunnel oxides and subsequently coated with a deposited SiO2 control dielectric. A range of temperatures in which we can adequately control a nucleation process, that gives rise to nanocrystal densities of ∼3×1011 cm−2 with good uniformity on the wafer, has been defined. The memory effects are observed in metal-oxide-semiconductor capacitors or field effect transistors by significant and reversible flat band or threshold voltage shifts between written and erased states that can be achieved by applying gate voltages as low as 5 V. The program-erase window does not exhibit any change after 105 cycles on large area cells showing that the endurance of such a memory device which uses a thinner tunnel oxide is potentially much higher than that of standard nonvolatile memories. Moreover, good retention results are ...

Nucleation kinetics of Si quantum dots on SiO2

The formation of Si quantum dots on SiO2 by chemical vapor deposition of SiH4 has been investigated in the range from the submonolayer to the complete coverage with Si. In order to investigate the very early stages of the nucleation process of Si on SiO2, the energy filtered transmission electron microscopy has been chosen as the main characterization technique, because of the high spatial resolution typical of the transmission electron microscopy analysis, coupled to the compositional information obtained by the electron energy loss spectroscopy. The plan view configuration has been used to measure the dot size distributions down to dimensions of about 1 nm, and in cross section to evaluate the dot wetting angle. For all the several experimental conditions, a wetting angle distribution has been obtained and has shown to be centered at about 90°. Data on the dot size distributions are shown and discussed in the framework of a continuous nucleation model, which has been implemented to take into account the...

Peculiar aspects of nanocrystal memory cells: data and extrapolations

Nanocrystal memory cell are a promising candidate for the scaling of nonvolatile memories in which the conventional floating gate is replaced by an array of nanocrystals. The aim of this paper is to present the results of a thorough investigation of the possibilities and the limitations of such new memory cell. In particular, we focus on devices characterized by a very thin tunnel oxide layer and by silicon nanocrystals formed by chemical vapor deposition. The direct tunneling of the electrons through the tunnel oxide, their storage into the silicon nanocrystals, and furthermore, retention, endurance, and drain turn-on effects, well-known issues for nonvolatile memories, are all investigated. The cell can be also programmed by channel hot electron injection, allowing the possibility to multibit storage. The suppression of the drain turn-on and the possibility of using this cell for multibit storage give us a clear evidence of the distributed nature of the charge storage.

Nanocrystal Memory Cell Integration in a Stand-Alone 16-Mb nor Flash Device

We report on the full process integration of nanocrystal (NC) memory cells in a stand-alone 16-Mb NOR Flash device. The Si NCs are deposited by chemical vapor deposition on a thin tunnel oxide, whose surface is treated with a low thermal budget process, which increases NC density and minimizes oxide degradation. The device fabrication has been obtained by means of conventional Flash technology, which is integrated with the CMOS periphery with high- and low-voltage transistors and charge pump capacitors. The memory program and erase threshold voltage distributions are well separated and narrow. The voltage distribution widths are related to NC sizes and dispersion, and bigger NCs can induce a cell reliability weakness. An endurance issue is also related to the use of an oxide/nitride/oxide dielectric which acts as a charge trapping layer, causing a shift in the program/erase window and a distribution broadening during cycling.

Localized charge storage in nanocrystal memories: feasibility of a multi-bit cell

We have realized Si nanocrystal memory cells in which the Si dots have been deposited by chemical vapor deposition (CVD) on the tunnel oxide and then covered by a CVD control oxide. In this paper we report a study on the potential of this type of cell for multi-bit storage. In particular, the possibilities offered by these devices from the point of view of program/erase mechanisms, endurance, and charge retention are shown and discussed.

Memory effects in MOS devices based on Si quantum dots

Abstract Silicon quantum dots have been deposited on top of a 3-nm tunnel oxide by Low Pressure Chemical Vapour Deposition (LPCVD) and coated with a 7-nm Chemical Vapour Deposited (CVD) oxide. This stack was then incorporated in Metal-Oxide-Semiconductor structure and used as floating gate of a memory cell. The presence of 3 nm of tunnel oxides allows the injection of the charge by direct tunnel (DT) using low voltages for both program and erase operations. The charge stored in the quantum dots is able to produce a well-detectable flat band shift in the capacitors or, equivalently, a threshold voltage shift in the transistors. Furthermore, due to the presence of SiO2 between the grains, the lateral charge loss is reduced and, thus, long retention time are possible. In this work we present good memory action characterised by low write voltages, write times of the order of milliseconds and long retention time in spite of the low tunnel oxide thickness.

Reliability and Retention Study of Nanocrystal Cell Array

We have studied nanocrystal memory arrays with 2.56 × 10 cells (256kb) in which Si nanocrystals have been obtained by CVD deposition on a 4nm tunnel oxide. The cells in the array are programmed and erased by electron tunneling through the SiO2 dielectric. We find that the threshold voltage distribution has little spread. In addition the arrays are also very robust with respect to drain stress and show good retention.