C. Himcinschi

Vapour-transport-deposition growth of ZnO nanostructures: switch between c-axial wires and a-axial belts by indium doping

Zn On anowires and nanobelts are two representatives of one-dimensional semiconductor nanomaterials possessing potential applications as optoelectronic and sensor devices. In this study, we applied a vapour-transport-deposition method to synthesize both types of nanostructures using relatively low temperatures (860 ◦ C) by controlling the source materials. We found that the resulting product under similar growth conditions can be switched between [0001]-axial nanowires and � 11 ¯ 20� -axial nanobelts simply by adding indium to the source. The former appear as ordered vertical arrays of pure ZnO while the latter are belts without spatial ordering. Both represent defect-free single crystals grown via the vapour–liquid–solid mechanism using nanosphere lithography-fabricated catalyst Au templates. Examination of the early growth stage suggests that the dissolution of In into Au influences the nucleation of ZnO at the solid–liquid interface, and subsequently defines the structure and crystallographic orientation of the nanobelts. The optical properties of both nanostructures are studied by photoluminescence and resonant Raman scattering, which indicate consistently that the doped nanobelts have a higher carrier concentration than the nanowires. (Some figures in this article are in colour only in the electronic version)

Strain relaxation in nanopatterned strained silicon round pillars

Periodic arrays of strained Si (sSi) round nanopillars were fabricated on sSi layers deposited on SiGe virtual substrates by electron-beam lithography and subsequent reactive-ion etching. The strain in the patterned sSi nanopillars was determined using high-resolution UV micro-Raman spectroscopy. The strain relaxes significantly upon nanostructuring: from 0.9% in the unpatterned sSi layer to values between 0.22% and 0.57% in the round sSi pillars with diameters from 100 up to 500nm. The strain distribution in the sSi nanopillars was analyzed by finite element (FE) modeling. The FE calculations confirm the strain relaxation after patterning, in agreement with the results obtained from Raman spectroscopy.

Strained Silicon on Wafer Level by Wafer Bonding: Materials Processing, Strain Measurements and Strain Relaxation

Different methods to introduce strain in thin silicon device layers are presented. Uniaxial strain is introduced in CMOS devices by process-induced stressors allowing the local generation of tensile or compressive strain in the channel region of MOSFETs. Biaxial strain is introduced by growing thin silicon layer on SiGe buffer and transferring it to an oxidized silicon substrates. The latter forms strained silicon on insulator (SSOI) wafer characterized by tensile strain only. Future CMOS device technologies require the combination of the global strain of SSOI substrates with local stressors to increase the device performance.

Compressive uniaxially strained silicon on insulator by prestrained wafer bonding and layer transfer

Wafer level compressive uniaxially strained silicon on insulator is obtained by direct wafer bonding of silicon wafers in cylindrically curved state, followed by thinning one of the wafers using the smart-cut process. The mapping of the wafer bow demonstrates the uniaxial character of the strain induced by the cylindrical bending. The interfacial properties are investigated by infrared transmission imaging, scanning acoustic microscopy, and transmission electron microscopy. UV-Raman spectroscopy is employed to determine the strain in the thin transferred layer as a function of radius of curvature of the initial bending.

Infrared spectroscopy of bonded silicon wafers

Infrared spectra of multiple frustrated total internal reflection and transmission for silicon wafers obtained by direct bonding in a wide temperature range (200–1100°C) are studied. Properties of the silicon oxide layer buried at the interface are investigated in relation to the annealing temperature. It is shown that the thickness of the SiO2 layer increases from 4.5 to 6.0 nm as the annealing temperature is increased. An analysis of the optical-phonon frequencies showed that stresses in the SiO2 relax as the annealing temperature is increased. A variation in the character of chemical bonds at the interface between silicon wafers bonded at a relatively low temperature (20–400°C) is studied in relation to the chemical treatment of the wafers’ surface prior to bonding. Models of the process of low-temperature bonding after various treatments for chemical activation of the surface are suggested.

Comparison of SiGe Virtual Substrates for the Fabrication of Strained Silicon-On- Insulator (sSOI) Using Wafer Bonding and Layer Transfer

Different methods of preparing sSOI wafers have been analyzed. The initial virtual substrate wafers are characterized by a 17 20 nm thick strained silicon layer grown either on a thick relaxed SiGe layer on a graded buffer or on a thin SiGe buffer relaxed by He implantation. Bonding and layer transfer experiments using different oxide layers proved that strained silicon layers are completely transferred if designed PE-CVD oxide layers were used. For both types of virtual substrates the oxide layers are deposited on top of the strained silicon and bonded to non-oxidized (blank) silicon wafers. A perfect layers transfer is obtained for virtual substrates having thick SiGe buffer layers (type A) even at 350°C, while annealing at 450 °C is required for substrates with thin SiGe buffer layers (type B). The lower annealing temperature for substrates of type A is caused by the lower activation energy for blistering. The hydrogen implantation is here into the SiGe. For type B substrates the hydrogen implantation is into the underlying Si requiring a higher temperature for layer splitting (higher activation energy for Si).