C.K. Oh

Front-end processing defect localization by contact-level passive voltage contrast technique and root cause analysis

To keep the evidence of the root cause, focused ion beam (FIB) cross-section and transmission electron microscope (TEM) analysis are the effective techniques for further analysis when a unit is de-processed to contact-level and front-end layers are still intact. To make sure that FIB cross-section hits a defect, it is very important to localize the defect precisely in advance. Since the contacts are the only access to the front-end layers of a semiconductor device, it should be possible to utilize them as probes to pinpoint the defects related to the front-end processes. In this paper, The technique of contact-level passive voltage contrast was employed to identify the contacts with abnormal contrast and thus localize the front-end processing defects.

Copper corrosion issue and analysis on copper damascene process

As semiconductor device features shrink into deep-submicron regime, copper metallization is taking the place of aluminum (Al)-tungsten (W) metallization because of the higher electrical conductivity and electromigration resistance of copper. However, it is very difficult for copper to be etched by dry etching method, thus copper metallization is created with damascene process. In this process, chemical mechanical polishing (CMP) is the key step. The wet chemical treatment in CMP makes copper corrosion to be one of the critical issues for copper metallization. This paper has addressed the three different types of copper corrosion, namely copper chemical corrosion, copper galvanic corrosion and photo assistant copper corrosion. The failure analyses for how to differentiate them and identify their root causes have been also discussed in details.

Study and application of wright etch in sub-quarter-micron technology

It is a well-known fact that stacking faults and crystalline defects in silicon wafers have impact the yield of the wafers. However as microelectronic devices scale down into deep sub-micron regime, there are reduction in the feature sizes of the transistors. This reduction in feature sizes has determine the size of the defect that have impact on the devices. In this paper, the timing of wright etch to correctly delineate stacking faults and silicon defects on chips of different technologies was evaluated. The application of wright etch to delineate the silicon defect localized by contact-level passive voltage contrast (PVC) technique in 0.18/spl mu/m and 0.13/spl mu/m technologies would be discussed too. This kind of silicon defect was also confirmed by cross-sectional transmission electron microscope analysis (XTEM).

Unique defects and analyses with copper damascene process for multilevel metallization

In this paper, we present some defects encountered and the involved failure analysis methods for these defects during copper metallization development.

A new paradigm of using TEM in yield enhancement failure analysis for sub-micron integrated circuit devices

Transmission electron microscope (TEM) has evolved from awkward-to-operate instrument into microprocessor-controlled instrument with various detectors attached. Improvement in the sample preparation from mechanical polishing to focused ion beam (FIB) assisted polishing has greatly improved the cycle time from days to few hours, enabling TEM is used as an essential tool in wafer fabrication plant. It is initially used as a process characterization tool, but the fast advancement of sub-micron integrated circuit has emerged TEM as essential equipment in yield enhancement failure analysis. As yield loss is increasingly dependent on critical features such as contacts and vias, conventional inspection method by scanning electron microscope (SEM) after deprocessing becomes constraint. Top down deprocessing follows by SEM examination cannot explain the root cause and it must depend on TEM to observe the detail of defect clearly. The role of SEM also evolves from inspection to passive voltage oriented. In other words, extensive voltage contrast is needed especially in stacked vias or contact. This paper explains the paradigm shift from conventional SEM examination analysis to TEM analysis. A few cases studies are presented to clarify this new paradigm.

Failure Analysis of A Unique Poly Defect

To successfully identify the root cause of a failure, it is required to have systematic failure analysis approaches with the right techniques and to make detailed observation during the course of analysis. In this paper, detailed failure analysis has been present to identify the root cause of a unique poly defect through taking the right approaches and techniques.

Application of Focus Ion Beam Circuit Edit in Failure Analysis

Focus ion beam is an indispensable tool in failure analysis laboratory. It has a wide range of applications. This paper will discuss its application in circuit edit to enhance failure analysis on two failure modes by isolating the defective sites of the failures and finally identifying the root causes.

A new and effective method in failure analysis of gate oxide polysilicon capacitor structure

In wafer fabrication, gate oxide integrity (GOI) plays an important role in the reliability and yield of integrated circuits. Failure in gate oxide polysilicon capacitor during reliability test and product manufacturing testing is a concern and needs failure analysis to determine the root cause of the failure. The most common method to perform fault isolation is using emission microscope to detect the emission spot. The challenging area to identify the defect in gate oxide polysilicon capacitor is the difficulty in removing bulk polysilicon of the structure. Although polysilicon etchant and acetone tape are used extensively, it always does not guarantee to successfully remove the polysilicon and most of time the success rate is low time consuming as it requires long time to delayer the structure. Thus in this paper a method was developed and bulk polysilicon can be etched in few seconds and the whole process of deprocessing can be completed in few minutes, greatly enhance the efficiency of performing failure analysis and resolves the difficulty encountered in Chartered. This method consists of dipping sample in SCI solution (1NH/sub 4/OH:1H/sub 2/O/sub 2/:5H/sub 2/O) follows by polysilicon etch (20HNO/sub 3/:8CH/sub 3/COOH:1HF).

Failure analysis on wafer edge issue in 0.13/spl mu/m technology

In this paper, two front ends and one back end issues which were found to have cause failure at the edge of wafers on 0.13/spl mu/m technology would be discussed. They are contact W-extrusion, STI gap-fill issue and Cu puddle due to thin film particle.

Application of sodium hydroxide in analysis of gate oxide issue of leakage failures

Continuous scale-down of advanced ULSI CMOS technologies has resulted in the corresponding thinning of the gate-oxide thickness in wafer fabrication. Such ultra thinner gate oxide will be more vulnerable to GOI (gate oxide integrity) failures. Potassium hydroxide (KOH) has been reported to be the choice of chemical for etching poly (Chen et al., 1995). But it is so aggressive that over-etch often happens, especially for ultra-thin gate oxide. Thus, in this paper we discuss on the application of sodium hydroxide (NaOH), which has shown a better result for units with I/O (input/output) pin leakage failures. Poly was removed completely without attacking the underlying gate-oxide, and thus it enables us to characterize the physical defects of gate oxide.