S.P. Neo

Copper corrosion issue and analysis on copper damascene process

As semiconductor device features shrink into deep-submicron regime, copper metallization is taking the place of aluminum (Al)-tungsten (W) metallization because of the higher electrical conductivity and electromigration resistance of copper. However, it is very difficult for copper to be etched by dry etching method, thus copper metallization is created with damascene process. In this process, chemical mechanical polishing (CMP) is the key step. The wet chemical treatment in CMP makes copper corrosion to be one of the critical issues for copper metallization. This paper has addressed the three different types of copper corrosion, namely copper chemical corrosion, copper galvanic corrosion and photo assistant copper corrosion. The failure analyses for how to differentiate them and identify their root causes have been also discussed in details.

Failure analysis of 65nm technology node SRAM soft failure

In this paper, a real case of 65 nm technology node SRAM failure was studied. The failure of the SRAM is soft failure, so the traditional method was failed to localize the exact position of the failed transistor. To find the root cause, the biased current image-Atom Force Microscopy combined with Atom Force Probing was used to probe the failed cell of the SRAM to find one abnormal pass-gate transistor. Theoretical analysis combined with the probing result was performed to find the failure location. Then current image was used to confirm the failure location. According to the AFP result, TEM and EDX were performed along the active of the pass-gate. Incomplete silicidation was observed under the active contact which correlated well to the electrical analysis result.

Application of FIB Circuit Edit and Electrical Characterization in Failure Analysis for Invisible Defect Issues

As semiconductor process technology rapidly develops into deep-sub-micron or nanometer regime, the feature size of semiconductor devices continues to shrink down. As a result, the defect being able to cause a device malfunction is also becoming smaller and smaller, and even certain defect is invisible with high-resolution SEM or TEM. It makes conventional physical failure analysis (PFA) face a great challenge for deep-sub-micron processed devices and the PFA success rate decrease because of such tiny or invisible defects. Thus electrical failure analysis (EFA) is becoming more and more important. FIB circuit edit and electrical characterization can provide critical clues of the failure mechanism through diagnosing the behaviour of a suspected defective transistor even if the defect is invisible with high-resolution SEM and TEM. This paper has demonstrated its application in failure analysis for two cases of invisible defect issues

Application of FIB circuit edit combined with TIVA in advanced failure analysis

This paper presented a failure analysis methodology to overcome the difficulties of fault location encountered by pin leakage and some testing parameter failures in a mixed signal device. These types of failure generally cannot be solved by traditional electrical failure analysis methods.

Study and application of wright etch in sub-quarter-micron technology

It is a well-known fact that stacking faults and crystalline defects in silicon wafers have impact the yield of the wafers. However as microelectronic devices scale down into deep sub-micron regime, there are reduction in the feature sizes of the transistors. This reduction in feature sizes has determine the size of the defect that have impact on the devices. In this paper, the timing of wright etch to correctly delineate stacking faults and silicon defects on chips of different technologies was evaluated. The application of wright etch to delineate the silicon defect localized by contact-level passive voltage contrast (PVC) technique in 0.18/spl mu/m and 0.13/spl mu/m technologies would be discussed too. This kind of silicon defect was also confirmed by cross-sectional transmission electron microscope analysis (XTEM).

A new paradigm of using TEM in yield enhancement failure analysis for sub-micron integrated circuit devices

Transmission electron microscope (TEM) has evolved from awkward-to-operate instrument into microprocessor-controlled instrument with various detectors attached. Improvement in the sample preparation from mechanical polishing to focused ion beam (FIB) assisted polishing has greatly improved the cycle time from days to few hours, enabling TEM is used as an essential tool in wafer fabrication plant. It is initially used as a process characterization tool, but the fast advancement of sub-micron integrated circuit has emerged TEM as essential equipment in yield enhancement failure analysis. As yield loss is increasingly dependent on critical features such as contacts and vias, conventional inspection method by scanning electron microscope (SEM) after deprocessing becomes constraint. Top down deprocessing follows by SEM examination cannot explain the root cause and it must depend on TEM to observe the detail of defect clearly. The role of SEM also evolves from inspection to passive voltage oriented. In other words, extensive voltage contrast is needed especially in stacked vias or contact. This paper explains the paradigm shift from conventional SEM examination analysis to TEM analysis. A few cases studies are presented to clarify this new paradigm.

Failure Analysis of A Unique Poly Defect

To successfully identify the root cause of a failure, it is required to have systematic failure analysis approaches with the right techniques and to make detailed observation during the course of analysis. In this paper, detailed failure analysis has been present to identify the root cause of a unique poly defect through taking the right approaches and techniques.

Failure Analysis Approach in Memory Failure of SOI Devices

Silicon-on-insulator (SOI) is a sandwich structure consisting of a thin insulating layer, such as silicon dioxide or glass sandwiching between a thin layer of silicon (T-Si) and the silicon substrate. The incorporation of the insulating layer between the T-Si and the silicon substrate has greatly changed the front-end process of microelectronic devices and thus the approach of failure analysis would be different compared to that of bulk technology. In this paper, approaches to analyze the single bit failure and pair bit failure in memory failure of SOI wafers would be presented.

Front End Defects on Deep Submicron Devices

Front end defects are usually more intricate as compared to back end defects, and as technology scale down into deep submicron regime, failure analysis of the front end defect is becoming even more challenging due to the increase in complexity of the process. In this paper, failure analysis on three types of front- end defect has been discussed. These defects are cobalt silicide at poly sidewall causing active to poly bridging, amorphous layer under contact and broken silicide on poly line, which were observed on 90 nm SOI wafers.

Application of Focus Ion Beam Circuit Edit in Failure Analysis

Focus ion beam is an indispensable tool in failure analysis laboratory. It has a wide range of applications. This paper will discuss its application in circuit edit to enhance failure analysis on two failure modes by isolating the defective sites of the failures and finally identifying the root causes.