S. Redkar

Formation of cobalt silicide spikes in 0.18 μm complementary metal oxide semiconductor process

Co silicide spikes have been found in active contact salicidation in complementary metal oxide semiconductor devices during failure analysis by means of transmission electron microscopy examination. Scanning transmission electron microscopy, energy dispersive x-ray analysis and microdiffraction study revealed that these spikes are CoSi2 with an epitaxial relationship with Si of (111)CoSi2//(111)Si and [110]CoSi2//[110]Si. The formation of the CoSi2 spikes are suspected to be due to the presence of undesired SiOx residue between Co film and Si substrate which acts as a solid diffusion membrane to cause the Si rich phase CoSi2 to precipitate directly inside Si lattice.

Application of contact-level ion-beam induced passive voltage contrast in failure analysis of static random access memory

The demand for improvement of device speed and reduction of power consumption has driven semiconductor devices to be miniaturized continuously. To develop new process generations, static random access memory (SRAM) is often chosen as the process qualification vehicle because the quality and performance of SRAMs are direct reflections of high density and small feature size, and they are very sensitive to process variation. Therefore, analysis of SRAM failure is a critical time-to market path for process development. During sub-quarter micron process development, the integrity of high aspect ratio contacts was found to be a major concern. For contact defect analysis, focus ion beam (FIB) cross-sectioning is the best method. However, the problem remains of how to identify the defective contact. E-beam testing and optical beam-induced current (OBIC) techniques have been reported as tools for detecting defective contacts. However, few FA labs have such equipment. In this study, a novel technique of contact-level ion-beam induced passive voltage contrast was developed to identify defective contacts employing a FIB station, and its application was demonstrated by SRAM failure analysis.

Development of a rapid and automated TEM sample preparation method in semiconductor failure analysis and the study of the relevant TEM artifact

Abstract Automated TEM sample preparation using focused ion beam (FIB) followed by plucking has been proposed to be a fast and reliable method in semiconductor failure analysis with extremely short cycle time needs. Artifacts caused by sample supporting film to image quality, energy dispersive X-ray (EDX) and electron energy loss spectrum (EELS) analysis are discussed. Damage (amorphizing) to sample surface induced by Ga + ion beam implantation during Pt protection film deposition was proved by TEM observation, and the method to avoid this damage are proposed.

Front-end processing defect localization by contact-level passive voltage contrast technique and root cause analysis

To keep the evidence of the root cause, focused ion beam (FIB) cross-section and transmission electron microscope (TEM) analysis are the effective techniques for further analysis when a unit is de-processed to contact-level and front-end layers are still intact. To make sure that FIB cross-section hits a defect, it is very important to localize the defect precisely in advance. Since the contacts are the only access to the front-end layers of a semiconductor device, it should be possible to utilize them as probes to pinpoint the defects related to the front-end processes. In this paper, The technique of contact-level passive voltage contrast was employed to identify the contacts with abnormal contrast and thus localize the front-end processing defects.

Copper corrosion issue and analysis on copper damascene process

As semiconductor device features shrink into deep-submicron regime, copper metallization is taking the place of aluminum (Al)-tungsten (W) metallization because of the higher electrical conductivity and electromigration resistance of copper. However, it is very difficult for copper to be etched by dry etching method, thus copper metallization is created with damascene process. In this process, chemical mechanical polishing (CMP) is the key step. The wet chemical treatment in CMP makes copper corrosion to be one of the critical issues for copper metallization. This paper has addressed the three different types of copper corrosion, namely copper chemical corrosion, copper galvanic corrosion and photo assistant copper corrosion. The failure analyses for how to differentiate them and identify their root causes have been also discussed in details.

Failure mechanism study for high resistance contact in CMOS devices

In advanced CMOS manufacturing, when aspects including contacts with W plugs are being miniaturised, high resistance contacts causing low yield becomes a common issue. In failure analysis, contact failures such due to insufficient trench etching and particle blocking which can cause extremely high resistance or opens are relatively easy to isolate and identify. However, for those contacts with resistance marginally higher than normal, the root cause is very difficult to identify by traditional methods like passive voltage contrast (PVC) and scanning electron microscopy (SEM), or focused ion beam (FIB) technology, which is quite successful for the open contact cases. This contact resistance variation is normally due to the narrow process window or process parameters drifting and may lead to relatively low yield. Direct observation of these contacts by transmission electron microscopy (TEM) provides detailed microstructural and chemical information which correlates to the failure and are unobtainable by other material analysis techniques. In this paper, we report a novel failure mechanism of the high resistance contact revealed by TEM study. Direct evidence is provided to show the impact of process changes on the contact structure which may correlate to the high resistance.

Application of passive voltage contrast and focused ion beam on failure analysis of metal via defect in wafer fabrication

A case of the application of passive voltage contrast (PVC) and focused ion beam (FIB) to failure analysis of metal interconnection or via defects in wafer fabrication was studied. We have proposed a simple, efficient and cost-saving identification method of locating the 1st, 2nd, 3rd and higher defective vias in the via chain through FIB-induced PVC and its precise cross-sectioning. Such a technique proves useful as it enables us to understand whether all the defective vias in the via chain exhibit the same failure phenomenon or display any particular failure pattern which will help the failure analysis or process engineers to determine the failure mechanism.

High resistance via induced by marginal barrier metal step coverage and F diffusion

In submicron multilevel metallization CMOS devices, high resistance vias and open via contacts are a common issue that can cause low yield and reliability problems (Islamraja et al., 1992). Via failure modes such as contaminated via, delaminated via and blown via contacts have been well documented (Hamanaka et al., 1994; Chen et al., 1995). Compared to the open via contact, a high resistance via due to insufficient process margin is more difficult to isolate and physically characterize. It has been reported that F contamination induces resistance variations and leads to timing issues in the SRAM (Perungulam et al., 2000). However, understanding of the F diffusion mechanism through the Ti-TiN barrier metal layer and the correlation with the barrier metal properties and thus the failure mechanism during reliability testing is still limited. In this paper, the failure mechanism of high via resistance caused by F diffusion was studied by transmission electron microscopy (TEM) at different process split steps. Properties of different barrier metal layers by different processes are also discussed.

High spatial resolution strain measurement of deep sub-micron semiconductor devices using CBED

Mechanical stress due to trench isolation and contact etch-stop-layers (ESLs) has been reported to show a marked influence on the electron and hole mobility of nanoscaled MOSFETs. Conventional tools such as micro-Raman spectroscopy and X-ray diffraction for measuring strain are limited in resolution. By using convergent beam electron diffraction (CBED) with nanometer spatial resolution, we have evaluated the mechanical stress induced in deep sub-micron devices by different etch-stop-layers (ESLs) and have demonstrated that the stress along the channel region can be engineered through the implementation of different ESLs.

A new fluorescent and Photoemission Microscope for submicron VLSI IC failure analysis

Photoemission Microscopy (PEM) has been widely used in modern VLSI IC failure analysis. As its camera normally detects the emissions from visible to near infrared light, it is more sensitive to non-heat-related failure such as junction related defect, gate oxide related defect, etc. As a complimentary technique, infrared photoemission microscope was developed by different companies or FA labs for heat-related defect fault isolation. However, its spatial resolution was limited due to the wavelength of the infrared light it used. This is especially a concern for submicron below VLSI technology. On the other hand, liquid crystal analysis (LCA) as an economical FA technique has been also used with great success for hot spot detection during IC failure analysis since 1980s. Nevertheless, its thermal sensitivity is also limited by the reduction of device operating voltage in deep submicron technology IC. To overcome the disadvantages of both techniques, in this paper, we developed a system by using one slow-scan CCD camera to detect both heat related and non-heat-related defects. The principle of analyzing the non-heat-related failure is same as that of PEM. For the heat-related defect, we use a chemical film (mixture of EuTTA and PMMA) under UV light excitation to convert the heat generated by the defect to fluorescent light of a peak at about 612 nm, which is able to be detected by the CCD camera. This is actually a kind of fluorescent microthermal imaging (FMI). The system based on such a concept was setup in our lab for submicron and deep submicron VLSI IC failure analysis. In this paper, comparison between the liquid crystal analysis and FMI also discussed.