C. L. Chan

Improved interface properties of p-type 6H–SiC/SiO2 system by NH3 pretreatment

Effects of preoxidation NH3 treatment on p-type 6H–SiC/SiO2 interface properties were investigated as compared to conventional thermally oxidized devices. It was found that NH3 treatment before oxidation can reduce the SiC/SiO2 interface states and fixed oxide charge. Furthermore, less shift of flatband voltage, and smaller increases of effective oxide charge and interface states during high-field stress were observed for the NH3 pretreated devices.

Improved electrical properties of Ge metal-oxide-semiconductor capacitor with HfTa-based gate dielectric by using TaOxNy interlayer

HfTa-based oxide and oxynitride with or without TaOxNy interlayer are fabricated on Ge substrate to form metal-oxide-semiconductor (MOS) capacitors. Their electrical properties and reliabilities are measured and compared. The results show that the MOS capacitor with a gate stack of HfTa-based oxynitride and thin TaOxNy interlayer exhibits low interface-state/oxide-charge densities, low gate leakage, small hysteresis, small capacitance equivalent thickness (∼0.94nm), and high dielectric constant (∼24). All these should be attributed to the blocking role of the TaOxNy interlayer against penetration of O into the Ge substrate and interdiffusions of Hf, Ge, and Ta, thus effectively suppressing the formation of unstable low-k GeOx and giving a superior TaOxNy∕Ge interface. Moreover, incorporation of N into both the interlayer and high-k dielectric greatly improves device reliability through the formation of strong N-related bonds.

Steam-induced interface improvement of N2O-nitrided SiO2 grown on 6H–SiC

Abstract Interface quality and reliability of n- and p-type 6H–SiC MOS capacitors with dielectric prepared by wet N 2 O nitridation (bubbling N 2 O gas through de-ionized water at 95 °C) or dry N 2 O nitridation plus wet reoxidation were investigated. When compared with the conventional dry N 2 O nitridation, the two nitridation processes greatly reduce interface-state density and enhance reliability of both n- and p-SiC MOS devices. The involved physical mechanisms could be attributed to steam-enhanced out-diffusion of CO and removal of interstitial carbon as well as carbon clusters, steam-enhanced nitrogen passivation and steam-induced hydrogen passivation of dangling bonds and carbon-related traps at the interface. As a result, N 2 O nitridation with slight modification could still be a superior process for preparing high-quality gate dielectric of both n- and p-SiC MOS devices in the industry-preferred N 2 O environment.

Interface properties of N2O-annealed SiC metal oxide semiconductor devices

Abstract Dry-oxidized and N 2 O-annealed n-type 6H–SiC metal-oxide-semiconductor capacitors are investigated at room temperature using a high-frequency C – V technique. Lower oxide-charge and interface-state densities are observed in case of dry-oxidized device. Oxide reliability of the capacitors is also investigated under high-field stress. Compared to a dry-oxidized device, smaller change in interface-state density occurs for a nitrided device under high-field stress. On the other hand, positive flat-band shift of nitrided device is found to be larger after the stress, implying that the nitridation creates acceptor-type interface states and oxide traps in the device. In summary, N 2 O nitridation improves the SiO 2 /n-type 6H–SiC interface and oxide hardness against stress-induced damage.

Optimization of N content for Higk-k LaTiON gate dielectric of Ge MOS capacitor

Thin LaTiON gate dielectric is deposited on Ge (100) substrate by reactive co-sputtering of La2O3 and Ti targets under different Ar/N2 ratios of 24/3, 24/6, 24/12, and 24/18, and their electrical properties are investigated and compared. Results show that the LaTiON gate-dielectric Ge MOS capacitor prepared at an Ar/N2 ratio of 24/6 exhibits highest relative permittivity, smallest capacitance equivalent thickness, and best electrical characteristics, including low interface-state density, small C-V hysteresis and low gate leakage current. This is attributed to the fact that a suitable N content in LaTiON can effectively suppress the growth of low-k GeOx interfacial layer between LaTiON and Ge substrate.

Impacts of Ti content and annealing temperature on electrical properties of Si MOS capacitors with HfTiON gate dielectric

HfTiON gate dielectric is fabricated by reactive co-sputtering method followed by annealing in N2 ambient. The effects of Ti content and annealing temperature on the performances of HfTiON gate-dielectric Si MOS devices are investigated. Experimental results indicate that gate capacitance is increased with increasing Ti content. However, when the Ti/Hf ratio exceeds ∼1.75, increase of the gate capacitance becomes small. Surface roughness of the samples annealed at different temperatures is analyzed by AFM, and results show that high annealing temperature (e.g. 700 °C for 30 s) can produce smooth surface, thus resulting in low gate leakage current.

Fabrication and electrical characterization of MONOS memory with novel high- k gate stack

A novel high-k gate stack structure with HfON/SiO<inf>2</inf> as dual tunneling layer (DTL), AlN as charge storage layer (CSL) and HfAlO as blocking layer (BL) is proposed to prepare the charge- trapping type of MONOS non-volatile memory device by employing in-situ sputtering method. The memory window, program/erase and retention properties are investigated and compared with similar gate stack structure with Si<inf>3</inf>N<inf>4</inf>/SiO<inf>2</inf> as DTL, HfO<inf>2</inf> as CSL and Al<inf>2</inf>O<inf>3</inf> as BL. Results show a large memory window of 3.55 V at P/E voltage of +8 V/-15 V, high program/erase speed and good retention characteristic can be achieved using the novel Au/ HfAlO/AlN/(HfON/SiO<inf>2</inf>)/Si gate stack structure. The main mechanisms lie in the enhanced electron injection through the high-k HfON/SiO<inf>2</inf> DTL, high trapping efficiency of the high-k AlN material and effective blocking role of the high-k HfAlO BL.