C.L. Lou

A new DC Drain-Current-Conductance method (DCCM) for the characterization of effective mobility (μ/sub eff/) and series resistances (R/sub s/, R/sub d/) of fresh and hot-carrier stressed graded junction MOSFETs

A simple new DC technique is developed to extract the gate bias dependent effective channel mobility (u/sub eff/) and series resistances (R/sub s/ and R/sub d/) of graded junction n- and p-channel MOSFETs. This technique is found to be accurate and effective for devices with differing channel lengths and also for devices after nonuniform hot-carrier degradation. The parameter values extracted provide further insight into the damage mechanisms of hot-carrier stressed graded junction nMOSFETs and are usable in circuit and reliability simulation. This technique is especially useful for the optimization of hot-carrier resistant structures of submicrometer MOSFETs.

Modelling the degradation in the subthreshold characteristics of submicrometre LDD PMOSFETs under hot-carrier stressing

Hot-carrier injection is observed increasingly to degrade the subthreshold characteristics with the scaling of LDD PMOSFETs. A physical subthreshold current model is applied to the fresh and hot-carrier-stressed submicrometre channel length devices. The channel length reduction is subsequently extracted. An empirical relationship is developed to characterize the degradation parameters as a function of stress time and channel length. With the use of this relationship, we can determine the device lifetime or predict the minimum allowable channel length (for a certain percentage of degradation and lifetime) that is applicable for a specific technology. The degradation of the PMOSFET subthreshold current, which imposes a major limit on device reliability for deep-submicron technology and low-power applications, is fully described by a physical analytical model.

Hot-carrier reliability of non-degenerately doped tungsten polycide gate buried-channel p-MOSFETs

Abstract A polysilicon-depletion effect is observed for the non-degenerately doped polysilicon layer of a tungsten silicide-polysilicon gate stack of buried-channel p -MOSFETs, but not for n -MOSFETs with a polysilicon layer of the same doping concentration. A lower current drive and transconductance, coupled with a higher subthreshold slope, will result in poorer dynamic performance for p -MOSFETs having a lower doped polysilicon layer. The potential drop across the lower doped polysilicon layer results in lower gate currents. Consequently the p -MOSFETs with a lower doped polysilicon layer are more resistant to hot-carrier induced degradation and have higher hot-carrier lifetimes. Thus there exists an optimum polysilicon doping concentration for tungsten-polycide devices and the latter is dependent on the desired electrical performance and hot-carrier reliability of buried-channel p -MOSFETs.

Hot-carrier induced degradation of polysilicon and tungsten polycide gate MOSFETs under maximum substrate and gate current stresses

Under maximum substrate current stress (i.e. ), the hot-carrier induced degradation of tungsten polycide gate n-MOSFETs in the linear drain current and maximum linear transconductance is lower, and the shift in the threshold voltage is higher than that of polysilicon gate (PolySi) n-MOSFETs. However, under maximum gate current stress (i.e. ), the n-MOSFETs showed higher hot-carrier induced degradation than the PolySi devices. In contrast, p-MOSFETs showed higher degradation compared with the PolySi p-MOSFETs under both (i.e. ) and (i.e. ) stresses. An explanation, substantiated by charge-pumping measurements, is proposed to explain the phenomena observed. The hot-carrier lifetime of p-MOSFETs is found to limit the operation of CMOS circuits.

Series resistance and effective channel mobility degradation in LDD nMOSFETs under hot-carrier stressing

With the ability to independently extract the series drain resistance and effective channel mobility from a single MOSFET device, the individual effect of these two parameters on the hot-carrier degradation in graded-drain nMOSFETs was separated and investigated. A self-limiting behaviour due to trapped charge and interface state generation was observed. A three-stage degradation model was proposed to explain the observed hot-carrier degradation behaviour.

Effective channel mobility and series resistance extraction for fresh and hot-carrier stressed graded junction MOSFETs using a single device

We present a new measurement technique-the drain current-conductance method (DCCM) to extract the gate-bias dependent effective channel mobility (/spl mu//sub eff/) and series resistances (R/sub s/ and R/sub d/) of drain-engineered MOSFETs. Experimental verification for devices with differing channel lengths and after hot-carrier stresses showed that this technique is accurate and effective. The parameters extracted has provided further insight into the asymmetries of graded junctions, and the damage mechanisms of hot-carrier degraded MOSFETs.

Modelling the hot-carrier induced degradation in the subthreshold characteristics of submicrometer LDD PMOSFETs

Hot-carrier injection is observed to increasingly degrade the subthreshold characteristics with the scaling of LDD PMOSFETs. A physical subthreshold current model is applied to the fresh and hot-carrier stressed submicrometer channel length devices. The generated interface traps and channel length reduction are subsequently extracted. An empirical model is developed to characterize the degradation parameters as a function of stress time and channel length. With the use of this model, we can determine the degradation parameters and hence predict the minimum allowable channel length (for a certain percentage of degradation and lifetime) that is applicable for a specific technology.

Characterization Of The Plasma-induced Effective Mobility Degradation Of LATID NMOSFETs

The effective mobility of NMOSFETs with different plasma damage is characterized by a new technique. The applicability of this technique is verified. The effective mobility is observed to be more sensitive than the maximum linear transconductance as a measure of the quality of the Si-Si02 interface.

Hot-carrier reliability of n- and p- channel MOSFETS with polysilicon and CVD tungsten-polycide gate

Under maximum substrate current (I/sub sub,max/) stress, tungsten-polycide gate (WS/sub x/) n-MOSFETs are more resistant to hot-carrier degradation than polysilicon gate (PolySi) devices. However, under maximum gate current (I/sub g,max/) stress, WSi/sub x/ n-MOSFETs degrade more severely. WSi/sub x/ p-MOSFETs degrade more than the PolySi p-MOSFETs under both the I/sub sub,max/ and I/sub g,max/ stress. An explanation substantiated by the charge-pumping measurements is proposed. The hot-carrier lifetimes of WSi/sub x/ n-MOSFETs are found to be higher than that of the WSi/sub x/ p-MOSFETs.

A comparative study on the channel hot-carrier degradation of N- and P-MOSFETs with CVD tungsten polycide gate

The channel hot-carrier induced degradation of polysilicon (PolySi) and tungsten polycide (WSi/sub x/) gate nMOSFETs and pMOSFETs are studied using the charge-pumping (CP) technique. WSi/sub x/ nMOSFETs under maximum substrate current (I/sub sub,max/) stress (V/sub g//spl sime/V/sub d//2) are degraded to a smaller extent when compared to the PolySi nMOSFETs. From the CP measurements, it is confirmed that fewer interface traps (N/sub it/) are generated for the WSi/sub x/ devices. However, under maximum gate current (I/sub g,max/) stress (V/sub g/=V/sub d/), the WSi/sub x/ nMOSFETs showed higher degradation than the PolySi devices. In contrast, WSi/sub x/ pMOSFETs showed higher degradation when compared to the PolySi devices under both the I/sub g,max/ and I/sub sub,max/ stresses. The CP results showed that more N/sub it/ and N/sub ox/ (negative oxide trapped charges) are present in the WSi/sub x/ pMOSFETs when compared with the PolySi devices. Finally, the operation of WSi/sub x/ CMOS transistors is found to be limited by the hot-carrier lifetime of WSi/sub x/ pMOSFETs.