D.S.H. Chan

Effect of surface NH3 anneal on the physical and electrical properties of HfO2 films on Ge substrate

Metal-oxide-semiconductor capacitors were fabricated on germanium substrates by using metalorganic-chemical-vapor-deposited HfO2 as the dielectric and TaN as the metal gate electrode. It is demonstrated that a surface annealing step in NH3 ambient before the HfO2 deposition could result in significant improvement in both gate leakage current and the equivalent oxide thickness (EOT). It was possible to achieve a capacitor with an EOT of 10.5 A and a leakage current of 5.02×10−5 A/cm2 at 1 V gate bias. X-ray photoelectron spectroscopy analysis indicates the formation of GeON during surface NH3 anneal. The presence of Ge was also detected within the HfO2 films. This may be due to Ge diffusion at the high temperature (∼400 °C) used in the chemical-vapor deposition process.

Fermi pinning-induced thermal instability of metal-gate work functions

The dependence of the metal-gate work function on the annealing temperature is experimentally studied. We observe increased Fermi-level pinning of the metal-gate work function with increased annealing temperature. This effect is more significant for SiO/sub 2/ than for HfO/sub 2/ gate dielectric. A metal-dielectric interface model that takes the role of extrinsic states into account is proposed to explain the work function thermal instability. This letter provides new understanding on work function control for metal-gate transistors and on metal-dielectric interfaces.

Alternative surface passivation on germanium for metal-oxide-semiconductor applications with high-k gate dielectric

An alternative surface passivation process for high-k Ge metal-oxide-semiconductor (MOS) device has been studied. The surface SiH4 annealing was implemented prior to HfO2 deposition. X-ray photoelectron spectroscopy analysis results show that the SiH4 surface passivation can greatly prevent the formation of unstable germanium oxide at the surface and suppress the Ge out-diffusion after the HfO2 deposition. The electrical measurement shows that an equivalent oxide thickness of 13.5A and a leakage current of 1.16×10−5A∕cm2 at 1V gate bias was achieved for TaN∕HfO2∕Ge MOS capacitors with the SiH4 surface treatment.

A TaN-HfO/sub 2/-Ge pMOSFET with NovelSiH/sub 4/ surface passivation

In this letter, we demonstrate a novel surface passivation process for HfO/sub 2/ Ge pMOSFETs using SiH/sub 4/ surface annealing prior to HfO/sub 2/ deposition. By using SiH/sub 4/ passivation, a uniform amorphous interfacial layer is formed after device fabrication. Electrical results show that the HfO/sub 2/ Ge MOSFET with Si-passivation exhibits less frequency dispersion, narrower gate leakage current distribution, and a /spl sim/140% higher peak mobility than that of the device with surface nitridation.

Schottky-barrier S/D MOSFETs with high-k gate dielectrics and metal-gate electrode

This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-/spl kappa/ gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D) , excellent electrical performance of I/sub on//I/sub off//spl sim/10/sup 7/-10/sup 8/ and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi/sub 2-x/ S/D , I/sub on//I/sub off/ can reach /spl sim/10/sup 5/ at V/sub ds/ of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-/spl kappa/ dielectric and metal-gate materials to be used in the future generation CMOS technology.

Performance breakthrough in 8 nm gate length Gate-All-Around nanowire transistors using metallic nanowire contacts

Parasitic S/D resistances in extremely scaled GAA nanowire devices can pathologically limit the device drive current performance. We demonstrate for the first time, that S/D extension dopant profile engineering together with successful integration of low resistivity metallic nanowire contacts greatly reduces parasitic resistances. This allows 8 nm gate length GAA nanowire devices in this work to attain record-high drive currents of 3740 muA/mum.

Simple tandem organic photovoltaic cells for improved energy conversion efficiency

We proposed and demonstrated a simple tandem structure of organic photovoltaic (PV) cell for efficient light harvesting. In this device structure, a soluble fullerene derivative of [6,6]-phenyl-C61-butyric acid methyl ester (PCBM) is employed simultaneously to form a bilayer heterojunction PV subcell with the underlying copper phthalocyanine (CuPc) and a bulk heterojunction PV subcell with blended poly(3-hexylthiophene-2,5-diyl) (P3HT). In comparison with the conventional tandem structure, the omission of the semitransparent intercellular connection layer reduces the complexity of the device and the light loss. The enhanced short circuit current density (JSC=8.63mA∕cm2) and power conversion efficiency (PCE) (2.79%) of the tandem structure are nearly the sum of those of the stand-alone cells of CuPc/PCBM (JSC=2.09mA∕cm2, PCE=0.43%) and P3HT:PCBM (JSC=6.87mA∕cm2, PCE=2.50%).

Thermal stability of nitrogen incorporated in HfNxOy gate dielectrics prepared by reactive sputtering

In this letter, we report the thermal stability of nitrogen incorporated in HfOxNy gate dielectrics prepared by reactive sputtering using x-ray photoelectron spectroscopy, secondary ions mass spectrometry, and electrical characterization. The results indicate that the bulk Hf–N bonds in reactive-sputtered HfOxNy are not stable during the postdeposition annealing and can be easily replaced by oxygen, resulting in significant loss of nitrogen from the bulk film. However, N at the HfOxNy/Si interface forms N–Si bonds, contributing to the excellent electrical stability of reactive sputtered HfOxNy gate dielectrics during the post deposition annealing.

Fermi-level pinning induced thermal instability in the effective work function of TaN in TaN/SiO/sub 2/ gate stack

In this letter, we demonstrate for the first time that the Fermi-level pinning caused by the formation of Ta(N)-Si bonds at the TaN/SiO/sub 2/ interface is responsible for the thermal instability of the effective work function of TaN in TaN/SiO/sub 2/ devices after high temperature rapid thermal annealing (RTA). Because of weak charge transfer between Hf and Ta(N) and hence negligible pinning effect at the TaN/HfO/sub 2/ interface, the effective work function of TaN is significantly more thermally stable on HfO/sub 2/ than on SiO/sub 2/ dielectric during RTA. This finding provides a guideline for the work function tuning and the integration of metal gate with high-/spl kappa/ dielectric for advanced CMOS devices.

Electrically Bistable Thin-Film Device Based on PVK and GNPs Polymer Material

We present an electrical-bistability device based on MIM-sandwiched structure. Poly(N-vinylcarbazole) (PVK) mixed with gold nanoparticles (GNPs) serve as the active layer between two metal electrodes. After applying a voltage, the as-fabricated device can transit from low conductivity state to high conductivity state. By simply using a reverse bias, the high conductivity state can return to the low conductivity state. An on/off current ratio as high as 105 at room temperature has been achieved. The memory effect is attributed to electric-field-induced charge transfer complex formed between the PVK and the GNPs. The device shows a good stability under stress test for both states and exhibits a high potential on Flash-type memory applications