Wai Kin Chim

Observation of memory effect in germanium nanocrystals embedded in an amorphous silicon oxide matrix of a metal–insulator– semiconductor structure

The memory effect of a trilayer structure (rapid thermal oxide/Ge nanocrystals in SiO2/sputtered SiO2) was investigated via capacitance versus voltage (C–V) measurements. The Ge nanocrystals were synthesized by rapid thermal annealing of the cosputtered Ge+SiO2 films. The memory effect was manifested by the hysteresis in the C–V curve. Transmission electron microscope and C–V results indicated that the hysteresis was due to Ge nanocrystals in the middle layer of the trilayer structure.

Hafnium aluminum oxide as charge storage and blocking-oxide layers in SONOS-type nonvolatile memory for high-speed operation

The charge storage and program/erase mechanisms in polysilicon-oxide-nitride-oxide-silicon (SONOS) memory structures with charge-storage layers of different materials are investigated in this paper. In particular, the use of a HfAlO charge-storage layer in a SONOS-type memory structure is proposed. Compared to other high-/spl kappa/ charge-storage layers, HfAlO has the advantage of high-speed program/erase of HfO/sub 2/ as well as the good charge-retention time of Al/sub 2/O/sub 3/, which makes HfAlO a promising candidate for the charge-storage layer in a SONOS-type memory. The use of HfAlO with different HfO/sub 2/ and Al/sub 2/O/sub 3/ compositions as a blocking-oxide layer in SONOS-type structures is also investigated.

Traps in germanium nanocrystal memory and effect on charge retention: Modeling and experimental measurements

Surface traps, or traps at the interface of the nanocrystal and the surrounding matrix, play an important role in the charge retention performance of nanocrystal memory transistors. In this article, we report the investigation of trap energy levels in nanocrystalline germanium (nc-Ge) memory transistor and capacitor structures and their effect on the device charging and discharging kinetics through theoretical modeling and experimental measurements. The theoretical model, calibrated using the experimental data, uses a self-consistent quantum-mechanical tunneling numerical approach for calculating the transmission coefficient across the tunnel barrier. The effect of the trap energy on charge retention is shown by temperature-dependent measurements on the nc-Ge memory structures. The trap energy-level requirement for achieving a specified long-term charge retention performance (i.e., 10-yr retention time) is obtained from simulation as a function of the nanocrystal size.

A novel single-device DC method for extraction of the effective mobility and source-drain resistances of fresh and hot-carrier degraded drain-engineered MOSFET's

A new DC technique, the drain current-conductance method (DCCM), has been developed to extract the gate bias dependent effective channel mobility (/spl mu//sub eff/), and source and drain series resistance (R/sub s/ and R/sub d/) of drain-engineered MOSFETs. The extraction of /spl mu//sub eff/, R/sub e/, and R/sub d/ by DCCM is based on the DC measurements of drain current and conductance of a single device. The negligible difference between the measured and modeled (using the extracted parameters) linear drain current showed that the DCCM is accurate and effective for devices with different graded junction structures and channel lengths. Asymmetry between R/sub s/ and R/sub d/ for LDD p-MOSFETs was found to be more significant than for LATID n-MOSFETs. This asymmetry has invalidated many methods which utilized the assumptions of R/sub d/=R/sub s/ for the extraction of device parameters. The DCCM was further applied to devices with nonuniform hot-carrier degradation. The /spl mu//sub eff/, R/sub s/, and R/sub d/ of LATID n-MOSFETs degraded under different hot-carrier stress conditions were extracted. The increase in R/sub d/ is found to dominate the initial phase of hot-carrier degradation while the decrease in /spl mu//sub eff/ intensifies as the stress duration increases. The extracted parameters have provided physical insight into the asymmetries of graded junctions and degradation mechanisms of hot-carrier stressed MOSFETs, The DCCM is especially useful for the extraction of SPICE parameters that are usable in circuit and reliability simulation.

Extraction of metal-oxide-semiconductor field-effect-transistor interface state and trapped charge spatial distributions using a physics-based algorithm

In this article, a new charge-extraction algorithm is proposed for extracting the spatial distributions of hot-carrier-induced interface states and trapped charges in p- and n- metal-oxide-semiconductor field-effect transistors, based on the charge-pumping measurement data. This extraction algorithm is physics based and provides a better understanding of how the presence of hot-carrier-induced trapped charges and interface states affect the charge-pumping curves. The extraction time for this new algorithm is very fast (typically 30 s) and does not require very tedious computer simulation. The verification of this method was performed using TSUPREM-4 and MEDICI simulations. With this new extraction method, one can gain better insight into the degradation mechanisms taking place under different hot-carrier stressing conditions.

Size control and charge storage mechanism of germanium nanocrystals in a metal-insulator-semiconductor structure

The size of germanium (Ge) nanocrystals in a trilayer metal-insulator-semiconductor memory device was controlled by varying the thickness of the middle (co-sputtered Ge+SiO2) layer. From analyses using transmission electron microscopy and capacitance–voltage measurements, we deduced that both electrons and holes are most likely stored within the nanocrystals in the middle layer of the trilayer structure rather than at the interfaces of the nanocrystals with the oxide matrix.

Highly ordered CdS nanoparticle arrays on silicon substrates and photoluminescence properties

Highly ordered cadmium sulphide (CdS) nanoparticle (NP) arrays were fabricated on silicon (Si) substrates using ultrathin alumina membranes as evaporation masks. The CdS NPs are polycrystalline and are composed of ultrasmall closely packed nanocrystallites. These crystallites increase in size as the duration of the CdS evaporation process increases. When the thickness of the NPs changes from about 10 to 50 nm, the size of the crystallites increases from about 5–14 to 20–40 nm. Photoluminescence measurements on the CdS NP arrays show a strong emission spectrum with two subbands that are attributed to band-edge and surface-defect emissions. The peak position and width of the band-edge emission band are closely related to the size of the crystallites in the CdS NPs.

High-k HfAlO charge trapping layer in SONOS-type nonvolatile memory device for high speed operation

A HfAlO charge storage layer in SONOS (polysilicon-oxide-silicon nitride-oxide-silicon)-type memory with a SiO/sub 2//high-K/SiO/sub 2/ (SOHOS) structure is proposed. Compared to other high-K charge storage layers, HfAlO shows the advantages of high speed program/erase of HfO/sub 2/ as well as good charge retention of Al/sub 2/O/sub 3/, which makes HfAlO the most promising candidate for the charge storage layer. The charge storage and program/erase mechanisms of different charge storage layers in SONOS-type structures are also investigated.

Germanium diffusion and nanocrystal formation in silicon oxide on silicon substrate under rapid thermal annealing

The effect of rapid thermal annealing temperature on the diffusion of silicon (Si) and germanium (Ge) and the formation of Ge nanocrystals in a silicon oxide matrix was investigated. The formation of Ge nanocrystals was attributed mainly to the reduction of Ge suboxides by Si diffused from the Si substrate. For samples annealed at 800°C, the nanocrystals were uniform in size and distributed evenly in the bulk of the oxide but became denser nearer to the silicon–silicon oxide (Si–SiO2) interface. When the sample was annealed at 900°C, two regions with different nanocrystal densities and size distributions separated by a region void of nanocrystals were observed. The region of denser nanocrystals was located near the Si–SiO2 interface. For annealing at 1000°C, nanocrystals were only observed at the Si–SiO2 interface and these have significant size variation, with the rest of the oxide being void of nanocrystals. The nanocrystals formed at 900 and 1000°C were generally found to be defective.

Interfacial and bulk properties of zirconium dioxide as a gate dielectric in metal–insulator–semiconductor structures and current transport mechanisms

In this article, we show the structural and electrical characterization results on aluminum gate/zirconium dioxide/n-type silicon (Al/ZrO2/n-Si) metal–insulator–semiconductor (MIS) devices with equivalent-oxide thickness (EOT) of ∼2.5 nm. About 60% of the devices fabricated with the optimized process conditions showed leakage current density of less than 2 x 10−5 A/cm2 at 1 V accumulation bias, which is lower than devices with silicon dioxide as a gate dielectric of similar EOT. Transmission electron microscopy images showed a ∼1.7-nm-thick interfacial layer (possibly zirconium silicate) and a ∼13-nm-thick bulk ZrO2 layer for the sputter-deposited high-k film. The difference in the dc leakage current of individual devices is due to the varying degrees of crystallization of the bulk ZrO2 layer, and not related to the interface state density. It was found that the interfacial layer between the bulk ZrO2 and the silicon substrate plays an important role in determining the conduction mechanism through the hig...