C.L. Pettiette-Hall

High-T/sub c/ superconducting monolithic phase shifter

A high temperature superconducting (HTS) X-band phase shifter using a distributed Josephson inductance (DJI) approach was designed and fabricated. Phase swings of over 60 degrees were measured at 65 K and below, with measurable phase shifts at temperatures above 77 K. High quality HTS films and superconducting quantum interference devices (SQUIDs) were deposited by laser ablation. A total of 40 HTS step edge SQUIDs were successfully integrated into a monolithic HTS circuit to produce a phase shifter in a resonant configuration. The magnitude of the Josephson inductance is calculated and a lumped element model is compared to measurements.<<ETX>>

YBCO step edge junctions on various substrates

We have fabricated YBCO 90/spl deg/ grain boundary junctions on step edges in NdGaO/sub 3/ and in deposited dielectric (CeO/sub 2/ on YSZ and SrTiO/sub 3/ on MgO) in order to compare junction performance to our standard, LaAlO/sub 3/. Average I/sub c/R/sub n/ values at 77 K in the 300-400 /spl mu/V range were measured for 2 /spl mu/m step edge junctions on NdGaO/sub 3/, LaAlO/sub 3/, and SrTiO/sub 3//MgO. Junction I/sub c/ is greatly reduced with the CeO/sub 2//YSZ system. I/sub c/R/sub n/ values in the 300-400 /spl mu/V range were measured at 65 K for 4 /spl mu/m junctions.<<ETX>>

Novel monolithic phase shifter combining ferroelectrics and high temperature superconductors

Abstract We describe a monolithic phase shifter which combines the low loss of high temperature superconductivity (HTS) with the variable dielectric properties of a ferroelectric material SrTiO3. Phase shifts greater than 28 degrees per wavelength were observed around 30 K. Benefits of the combination of HTS and ferroelectric materials are described. The compatibility of YBa2Cu3O7-x and other ferroelectric materials is discussed.

Co-doped-YBCO SNS junctions for superconductive integrated circuits

We have established a high temperature superconductor SNS junction fabrication process and are reproducibly fabricating junctions whose behavior is rooted in the physics of the proximity effect. SNS edge junctions are being fabricated using YBa/sub 2/Cu/sub 2.8/Co/sub 0.2/O/sub 7-/spl delta// (Co-YBCO) as the normal barrier, and YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta// (YBCO) as the superconductor. In the small junction regime, the junctions have RSJ characteristics with I/sub c/R/sub n//spl sim/ 50 /spl mu/V at 77 K. Junction normal resistance values are consistent with known values of the barrier bulk resistivity and junction geometry, indicating that the interface resistance between YBCO and Co-YBCO is not significant. We have demonstrated I/sub c/ and R/sub n/ 1-/spl sigma/ spreads of 33% and 17%, respectively, for 6-junction strings. Barrier thickness and/or morphology variations appear to significantly contribute to these spreads.<<ETX>>

Superconducting Ba/sub 1-x/K/sub x/BiO/sub 3/ thin film by in-situ sputtering

Superconducting Ba/sub 1-x/K/sub x/BiO/sub 3/ thin films with T/sub c/ (R=0) as high as 29.2 K have been grown using off-axis RF magnetron sputtering. Films are routinely deposited with zero resistance between 25 K and 29 K. High pressure during deposition is considered to be responsible for higher-T/sub c/ films. The films grow epitaxially with

Capacitively shunted, hysteretic YBa/sub 2/Cu/sub 3/O/sub 7/ step-edge junctions

Hysteretic YBa/sub 2/Cu/sub 3/O/sub 7/ step-edge junctions on LaAlO/sub 3/ substrates have been fabricated by shunting intrinsically overdamped junctions with a monolithic capacitor. By comparing the I-V curves of junctions fabricated on the same substrate with and without capacitor counterelectrodes, the authors are confident that the observed hysteresis is due to the shunting capacitor. The capacitor consists of a dielectric layer (SrTiO/sub 3/ or LaAlO/sub 3/), deposited on the YBa/sub 2/Cu/sub 3/O/sub 7/ directly over the step-edge junction and an Ag counterelectrode. Capacitor counterelectrodes ranging in area from 10 mu m*30 mu m to 200 mu m*220 mu m have been investigated. Dielectric layers several tens of nanometers thick have been used. The inferred beta /sub c/ values are as large as 10 at 4 K and decrease with increasing temperature. At 65 K, beta /sub c/ of 1.3 was observed. The measured beta /sub c/ values are smaller than one would naively calculate. These differences are attributed to the usual limitations of lumped-element circuit analysis and resistive losses.<<ETX>>

HTS edge junction dependence on base electrode edge smoothness

A series of experiments were performed in a Taguchi experimental matrix to examine and compare critical fabrication process factors in junction electrical performance. Factors such as angle of HTS deposition by pulsed laser deposition (PLD), pre-cleaning and annealing dwell time prior to epitaxial depositions, and angle of film edges created by ion milling were examined. The most critical factor influencing junction performance was the inherent morphology and smoothness of the base electrode. Based on this we focused on improving base electrode film smoothness. Using this approach we reduced junction excess current by a factor of 5 to 10 as confirmed by subsequent wafer fabrications, improved technique was then integrated into our two-inch wafer process which incorporates automated stepping equipment providing deep sub-micron layer-to-layer alignment capability.

A low-inductance, low-I/sub c/ HTS junction process

One of the challenges In fabricating digital circuitry with high temperature superconductors (HTS) is in developing a reliable junction process. The requirements of this junction process include: low-parasitic inductance, well-targeted and reproducible total inductance, uniformity in I/sub c/ and R/sub n/, and also well-targeted I/sub c/ and I/sub c/R/sub n/ product greater than 300 /spl mu/V at 65 K. Junction inductance can be greatly reduced by fabrication above a groundplane. Yet the addition of a groundplane introduces fabrication issues such as film smoothness and maintenance of epitaxy through the multiple layers necessary. Step-edge junctions and SNS edge junctions with groundplanes are examined and compared through a Taguchi experimental design series. Process equipment modifications in our HTS foundry necessary to reach our fabrication goals are outlined.

Dielectric properties of SrTiO/sub 3/ thin films at low temperature

The authors have fabricated YBCO (or Ag)/SrTiO/sub 3//YBCO capacitors for low-frequency measurements and SrTiO/sub 3//YBCO/LaAlO/sub 3/ coplanar-waveguide end-coupled resonators for high-frequency measurements of the SrTiO/sub 3/ dielectric constant at low temperatures. From the capacitor measurements, values for the dielectric constant ranging from approximately 200 to 800 were obtained for films of various thicknesses. This behavior of the thin-film dielectric constant was found to differ from that of the bulk crystal.<<ETX>>

Monolithic HTS microwave phase shifter and other devices

We describe a monolithic high-temperature superconductor (HTS) phase shifter based on the distributed Josephson inductance (DJI) design integrated monolithically into a 10-GHz microstrip line. This microwave circuit incorporates >1000 HTS rf SQUIDS. Recent data demonstrate the performance of this broadband HTS circuit. We observed phase shifts greater than 150° in resonant structures, and 20° in broadband circuits. The nonlinear inductance of the superconducting transmission line can be used for other novel applications, including parametric amplification. A comparison of the DJI circuit to a series array of Josephson elements (used for pulse sharpening) will contrast these two new and exciting nonlinear transmission line circuits.