J. Luine

Fabrication of high current density Nb integrated circuits using a self-aligned junction anodization process

We have developed a self-aligned Nb/Al-AlO/sub x//Nb junction anodization process that allows outside junction contacts and relaxed contact alignment. In this process, the junction, rather than the junction contact, becomes the minimum definable feature size. Junction size is limited only by the resolution of the lithography and etch tools, which is 0.65 /spl mu/m in our foundry. The self-aligned junction anodization process allows a significant increase in circuit speed due to the decrease in minimum junction size and increase in junction critical current density without investment in new fabrication tools. This process requires only one additional, noncritical masking step and has no impact on existing design rules. We describe the fabrication and electrical characteristics of lightly anodized junctions and arrays at 8 kA/cm/sup 2/ and the development of new 5 /spl Omega//sq. MoN/sub x/ and 0.15 /spl Omega//sq. Mo/Al resistors. We also discuss the 300 GHz T flip-flop benchmark results from our new 8 kA/cm/sup 2/, 1.25 /spl mu/m Nb integrated circuit process and compare these results to other Nb processes.

Progress Towards a YBCO Circuit Process

We report on progress in several key areas necessary for the establishment of a circuit process for high-temperature superconductive electronics (HTSE). These include superconductor films, compatible dielectric layers, metallic contacts, and Josephson devices. Among the topics we cover are the properties of in situ YBCO films, the use of LaA1O3 as a thin film dielectric material, and the properties of several types of engineered microbridge structures that exhibit Josephson-effect behavior in high-quality films because of the introduction of localized disruption in the films.

YBCO step edge junctions on various substrates

We have fabricated YBCO 90/spl deg/ grain boundary junctions on step edges in NdGaO/sub 3/ and in deposited dielectric (CeO/sub 2/ on YSZ and SrTiO/sub 3/ on MgO) in order to compare junction performance to our standard, LaAlO/sub 3/. Average I/sub c/R/sub n/ values at 77 K in the 300-400 /spl mu/V range were measured for 2 /spl mu/m step edge junctions on NdGaO/sub 3/, LaAlO/sub 3/, and SrTiO/sub 3//MgO. Junction I/sub c/ is greatly reduced with the CeO/sub 2//YSZ system. I/sub c/R/sub n/ values in the 300-400 /spl mu/V range were measured at 65 K for 4 /spl mu/m junctions.<<ETX>>

10 K NbN DSP module for IR sensor applications

The authors report significant progress on infrared (IR) focal plane array (FPA) imaging signal processing circuits, built in NbN and operating at 10 K. The improvements to our NbN process are highlighted by the introduction of directly grounded junctions (DGJ). These DGJs substantially reduce parasitic inductance thereby compensating for the high sheet inductance of NbN films. The circuits being developed include a 16-bit SFQ counting ADC and several digital signal processing (DSP) units. We report test results of greatly improved ADC performance, which is the result of both improved designs and fabrication techniques. Signal processing units on individual chips have been designed, fabricated, and tested. They perform functions such as background subtraction, gain and responsivity correction, and data reduction. We report test results of the DSP chips performing these functions. Ultimately, these chips will be integrated on a multi-chip-module (MCM) with high bandwidth, low impedance interconnects and integrated with an IR focal plane array sensor.

Co-doped-YBCO SNS junctions for superconductive integrated circuits

We have established a high temperature superconductor SNS junction fabrication process and are reproducibly fabricating junctions whose behavior is rooted in the physics of the proximity effect. SNS edge junctions are being fabricated using YBa/sub 2/Cu/sub 2.8/Co/sub 0.2/O/sub 7-/spl delta// (Co-YBCO) as the normal barrier, and YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta// (YBCO) as the superconductor. In the small junction regime, the junctions have RSJ characteristics with I/sub c/R/sub n//spl sim/ 50 /spl mu/V at 77 K. Junction normal resistance values are consistent with known values of the barrier bulk resistivity and junction geometry, indicating that the interface resistance between YBCO and Co-YBCO is not significant. We have demonstrated I/sub c/ and R/sub n/ 1-/spl sigma/ spreads of 33% and 17%, respectively, for 6-junction strings. Barrier thickness and/or morphology variations appear to significantly contribute to these spreads.<<ETX>>

Capacitively shunted, hysteretic YBa/sub 2/Cu/sub 3/O/sub 7/ step-edge junctions

Hysteretic YBa/sub 2/Cu/sub 3/O/sub 7/ step-edge junctions on LaAlO/sub 3/ substrates have been fabricated by shunting intrinsically overdamped junctions with a monolithic capacitor. By comparing the I-V curves of junctions fabricated on the same substrate with and without capacitor counterelectrodes, the authors are confident that the observed hysteresis is due to the shunting capacitor. The capacitor consists of a dielectric layer (SrTiO/sub 3/ or LaAlO/sub 3/), deposited on the YBa/sub 2/Cu/sub 3/O/sub 7/ directly over the step-edge junction and an Ag counterelectrode. Capacitor counterelectrodes ranging in area from 10 mu m*30 mu m to 200 mu m*220 mu m have been investigated. Dielectric layers several tens of nanometers thick have been used. The inferred beta /sub c/ values are as large as 10 at 4 K and decrease with increasing temperature. At 65 K, beta /sub c/ of 1.3 was observed. The measured beta /sub c/ values are smaller than one would naively calculate. These differences are attributed to the usual limitations of lumped-element circuit analysis and resistive losses.<<ETX>>

HTS edge junction dependence on base electrode edge smoothness

A series of experiments were performed in a Taguchi experimental matrix to examine and compare critical fabrication process factors in junction electrical performance. Factors such as angle of HTS deposition by pulsed laser deposition (PLD), pre-cleaning and annealing dwell time prior to epitaxial depositions, and angle of film edges created by ion milling were examined. The most critical factor influencing junction performance was the inherent morphology and smoothness of the base electrode. Based on this we focused on improving base electrode film smoothness. Using this approach we reduced junction excess current by a factor of 5 to 10 as confirmed by subsequent wafer fabrications, improved technique was then integrated into our two-inch wafer process which incorporates automated stepping equipment providing deep sub-micron layer-to-layer alignment capability.

A low-inductance, low-I/sub c/ HTS junction process

One of the challenges In fabricating digital circuitry with high temperature superconductors (HTS) is in developing a reliable junction process. The requirements of this junction process include: low-parasitic inductance, well-targeted and reproducible total inductance, uniformity in I/sub c/ and R/sub n/, and also well-targeted I/sub c/ and I/sub c/R/sub n/ product greater than 300 /spl mu/V at 65 K. Junction inductance can be greatly reduced by fabrication above a groundplane. Yet the addition of a groundplane introduces fabrication issues such as film smoothness and maintenance of epitaxy through the multiple layers necessary. Step-edge junctions and SNS edge junctions with groundplanes are examined and compared through a Taguchi experimental design series. Process equipment modifications in our HTS foundry necessary to reach our fabrication goals are outlined.

High temperature performance of HTS step-edge DC SQUIDs

YBa/sub 2/Cu/sub 3/O/sub 7/ (YBCO) step edge DC superconducting quantum interference devices (SQUIDs) have been developed which exhibit characteristics suitable for near-term incorporation into high-temperature superconductive (HTS) circuitry. Step-edge junction DC SQUIDs for series array interferometer logic (SAIL) digital applications exhibit resistively shunted junction (RSJ) properties, 65 K I/sub c/ values of approximately 150 mu A, 65 K I/sub c/R/sub n/ values up to approximately 300 mu V, and large I/sub c/ modulation (>50%) in accordance with a standard DC SQUID model. 65 K SQUID switching voltages of approximately 100 mu V have been demonstrated and are sufficient for near-term applications of SAIL digital circuitry operating on a cryocooler platform.<<ETX>>

NbN and Nb SFQ device performance

The static frequency divider is commonly used as a performance benchmark for both superconductor and semiconductor digital device technologies. We present results of a static divide-by-two circuit, an NbN (1 kA/cm/sup 2/) SFQ T-flip-flop (TFF) operating to 97 GHz. Details of the measurement and operating criterion are discussed. Measurements of junction capacitance, a particularly important factor effecting device performance, are presented for TRWs NbN process. Simulations of expected device performance are shown to explain measured performance reasonably well. NbN results are presented alongside a those of a recent 8kA/cm/sup 2/ Nb divider operating at 300 GHz, as well as published Nb TFF results.