C. Leroux

Characterization and modeling of hysteresis phenomena in high K dielectrics

An original technique for the dynamic analysis of Id(Vg) hysteresis on high K stacks is proposed, allowing the characterization of Vt shift transients at short times. The experimental results demonstrate that trapping/de-trapping mechanism by tunneling from the substrate must be considered. Furthermore, a new model based on a trap-like approach is successfully developed to interpret the dependence of hysteresis phenomena with high k gate stack architecture.

75 nm damascene metal gate and high-k integration for advanced CMOS devices

An advanced CMOS process has been proposed which include key features: 75 nm gate length damascene metal gate, high-k dielectrics with 1.35 nm EOT. Detailed characterisation (TEM, C-V, split C-V, charge pumping, LF noise, low and high temperature transport) demonstrate the high quality of the dielectric and interface. Low Ioff and low gate current make the technology attractive for low standby power applications.

Frequency characterization and modeling of interface traps in HfSixOy/HfO2 gate dielectric stack from a capacitance point-of-view

A time-resolved analysis of the capacitance–voltage (C–V) technique and an inverse modeling approach have been developed to determine the energy distribution and the capture cross section of interface traps in the silicon band gap from multifrequency C–V measurements. In this work, our method is performed on n-type metal-oxide-semiconductor capacitors with HfSixOy/HfO2 gate dielectric stack and polysilicon gate. From the frequency dispersion of C–V data, we evidence a peak of acceptor states in the upper half of the band gap at 0.81 eV above the valence band and characterized by a capture cross section of 1.5×10−17 cm2. This value is approximately ten times lower than typical capture cross sections relative to the dangling bonds (Pb centers) at the Si/SiO2 interface, which is in good agreement with a Coulombic center model predicting a capture cross section inversely proportional to the square of the dielectric permittivity.

Characterization of effective mobility by split C(V) technique in N-MOSFETs with ultra-thin gate oxides

Reliable split C(V) measurements are shown to be feasible on ultra-thin oxides (down to 1.2 nm) by using relatively small area MOSFETs (typically 100 mum(2)). To this end, specific correction procedures for parasitic parallel capacitances and gate leakage impact on source-drain current characteristics are proposed. The amplitude of the effective mobility is found to be degraded significantly with oxide scaling. Moreover, the mobility attenuation at high field associated to the surface roughness remains unchanged with oxide thickness reduction. This mobility degradation could find its origin in enhanced remote coulomb or interface plasmon-phonon scattering processes, which are reinforced by oxide thinning

Electrical and physico-chemical characterization of HfO2/SiO2 gate oxide stacks prepared by atomic layer deposition

Abstract In this paper, we have correlated electrical measurements of thin HfO2 layers deposited on SiO2 by atomic layer deposition with angle-resolved X-ray photoelectron spectroscopy experiments. Results show that the HfO2/Si interface layer (IL) is made of a SiOx layer underneath a Si-rich Hf-silicate layer. The increasing of the IL thickness, during annealing, was essentially due to the silicon oxidation by –OH groups remaining in the HfO2 layer after deposition. Using shorter water pulse time, we were able to limit the SiOx growth during deposition. We have also observed, after annealing at 800 °C under nitrogen, a decreasing of the interfacial layer electrical thickness as well as an improvement of the equivalent oxide thickness of the stack.

Large-Scale Time Characterization and Analysis of PBTI In HFO2/Metal Gate Stacks

Many electrical properties of metal/high-k gate stack are dominated by defects. These defects play an important role in reliability issues in particular positive bias temperature instabilities (PBTI). In this paper, we investigate PBTI with a time resolved measurement technique allowing a large-scale time characterization. This technique allows us to separate different mechanisms, namely fast and slow trapping, newly slow stress-generated traps and finally positive charges. We clearly evidence which of them are or are not activated by temperature. We explain how to take into account these mechanisms for a precise lifetime extrapolation

An Efficient Model for Accurate Capacitance-Voltage Characterization of High-k Gate Dielectrics Using a Mercury Probe

An analytic electrical model for accurate capacitance-voltage (C-V) characterization of high-k gate dielectrics using a mercury probe is presented. This approach considers the series association of the dielectric/substrate impedance, the circuit series resistance, and an additional impedance modeling the interfacial layer between the oxide and the mercury-drop contact. This model is useful to describe the frequency behavior of C-V measurements in a wide range of frequencies (500 Hz to 100 kHz). The extraction procedure of model parameters is described and the method is successfully applied to high-k HfO 2 layers deposited on silicon with equivalent oxide thickness down to 1.2 nm.

Light emission microscopy for thin oxide reliability analysis

Abstract We present a wide analysis of light emission phenomenon in thin gate oxide. For thickness ranging from 45 to 230A, we study the dependence of photon emission rate with gate oxide thickness and gate materials. Soft breakdown occurring in ultra thin oxide is also analysed.

Initial and PBTI-induced traps and charges in Hf-based oxides/TiN stacks.

Abstract Positive voltage instabilities are studied for Nmos transistors with hafnium-based high-κ gate stacks. Using an optimized dedicated fast measurement setup, dynamic transient measurements of drain current are performed over more than ten decades of time. The two main phenomena involved, a reversible one known as hysteresis and a nonreversible one known as PBTI are clearly experimentally separated and studied in detail. A physical model is presented, explaining the dynamic behaviour and leading to precise traps physical characteristics and profiles inside the HfO2 layer. PBTI defects in HfO2 are shown to be of a different nature than hysteresis traps. A turn-around effect is evidenced for PBTI above which physical mechanisms seem to change; it has important implications on lifetime determination methodology. Finally, HfSiON experiments are presented for both hysteresis and PBTI and they show that this material is much less critical than HfO2.

New approach for the gate current source-drain partition modeling in advanced MOSFETs

Abstract A new approach for the modeling of the gate current source–drain partition is developed relying on a proper time response analysis of the MOSFET channel. The model enables to explain the non-uniformity along the channel and the gate length dependence of the gate current for MOSFETs with ultra thin oxides. Moreover, it provides a reasonably good description of the source and drain current transfer characteristics and corresponding partition gate currents in ohmic as well as in non-ohmic regions.