B. Guillaumot

Experimental and theoretical investigation of nano-crystal and nitride-trap memory devices

In this paper, we propose a thorough experimental and theoretical investigation of memory-cell structures employing discrete-trap type storage nodes, using either natural nitride traps or semiconductor nano-crystals. thus operating with a small finite number of electrons. A detailed account of static and dynamic charging/discharging phenomena occurring in these devices is given, based on bias-, time-, and temperature-dependent measurements. A comprehensive interpretation of experimental results is proposed by means of physical modeling. In particular, two different models are proposed. The first one consists in a modified floating-gate-like approach, while the second one is a trap-like approach, relying on Shockley-Read-Hall statistics. Using these two approaches, some general behavior laws for memory operation are formulated. Considerations on the suitability of each model on the particular structures are suggested.

Carrier transport in HfO/sub 2//metal gate MOSFETs: physical insight into critical parameters

Electron and hole mobility in HfO/sub 2//metal gate MOSFETs is deeply studied through low-temperature measurements down to 4.2 K. Original technological splits allow the decorrelation of the different scattering mechanisms. It is found that even when charge trapping is negligible, strong remote coulomb scattering (RCS) due to fixed charges or dipoles causes most of the mobility degradation. The effective charges are found to be located in the HfO/sub 2/ near the SiO/sub 2/ interface within 2 nm. Experimental results are well reproduced by RCS calculation using 7/spl times/10/sup 13/ cm/sup -2/ fixed charges at the HfO/sub 2//SiO/sub 2/ interface. We also discuss the role of remote phonon scattering in such gate stacks. Interactions with surface soft-optical phonon of HfO/sub 2/ are clearly evidenced for a metal gate but remain of second order. All these remote interactions are significant for an interfacial oxide thickness up to 2 nm, over which, these are negligible. Finally, the metal gate (TiN) itself induces a modified surface-roughness term that impacts the low to high effective field mobility even for the SiO/sub 2/ gate dielectric references.

75 nm damascene metal gate and high-k integration for advanced CMOS devices

An advanced CMOS process has been proposed which include key features: 75 nm gate length damascene metal gate, high-k dielectrics with 1.35 nm EOT. Detailed characterisation (TEM, C-V, split C-V, charge pumping, LF noise, low and high temperature transport) demonstrate the high quality of the dielectric and interface. Low Ioff and low gate current make the technology attractive for low standby power applications.

15nm-diameter 3D stacked nanowires with independent gates operation: ΦFET

For the first time, we report a 3D stacked sub-15 nm diameter NanoWire FinFET-like CMOS technology (3D-NWFET) with a new optional independent gate nanowire structure named PhiFET. Extremely high driving currents for 3D-NWFET (6.5 mA/mum for NMOS and 3.3 mA/mum for PMOS) are demonstrated thanks to the 3D configuration using a high-k/metal gate stack. Co-processed reference FinFETs with fin widths down to 6 nm are achieved with record aspect ratios of 23. We show experimentally that the 3D-NWFET, compared to a co-processed FinFET, relaxes by a factor of 2.5 the channel width requirement for a targeted DIBL and improves transport properties. PhiFET exhibits significant performance boosts compared to Independent-Gate FinFET (IG-FinFET): a 2-decade smaller IOFF current and a lower subthreshold slope (82 mV/dec. instead of 95 mV/dec.). This highlights the better scalability of 3D-NWFET and PhiFET compared to FinFET and IG-FinFET, respectively.

Carrier mobility in advanced CMOS devices with metal gate and HfO2 gate dielectric

Abstract Advanced channel N and P MOSFETs with HfO 2 gate dielectric and metal gate have been fabricated and exhibit high performance. The effective mobility has been characterized at various temperatures for NMOS and PMOS devices. The electron mobility is lower than in SiO 2 , whereas the hole mobility is relatively unaffected at room temperature but also degraded at low temperatures. The mobility degradation after constant voltage stress suggests a more important Coulomb scattering contribution to mobility as compared to SiO 2 .

Analog/RF Performance of Multichannel SOI MOSFET

In this paper, for the first time, we present a detailed RF experimental and simulation study of a 3-D multichannel SOI MOSFET (MCFET). Being different from the conventional planar technology, the MCFET features a total of three self-aligned TiN/HfO2 gate stacks fabricated on top of each other, allowing current to flow through the three undoped ultrathinned silicon bodies (UTBs). In other words, the operation of the MCFET is theoretically based on two UTB double-gate SOIs and a single-gate UTB fully depleted SOI (FDSOI) at the bottom. Using on-wafer S-parameters, the RF/analog figures-of-merit of an MCFET with a gate length of 50 nm are extracted and discussed. Thanks to the enormous transconductance (gm) and very low output conductance, the RF/analog performances of MCFET-voltage gain (A VI) and early voltage (V EA) are superior compared with that of the single-gate UTB-FDSOI. However, these advantages diminish in terms of transition frequency (fT), due to the large total input gate capacitances (C GG). This inspires the introduction of spacer engineering in MCFET, aiming at improving both C GG and fT. The sensitivity of the spacer length to the RF/analog performances is experimentally analyzed, and the performance optimization is validated using ac simulation. This paper concludes that optimized MCFETs are a serious contender to the mainstream MOSFETs including FinFETs for realizing future low-power analog applications.

Fabrication and mobility characteristics of SiGe surface channel pMOSFETs with a HfO/sub 2//TiN gate stack

This paper describes an extensive experimental study of TiN/HfO/sub 2//SiGe and TiN/HfO/sub 2//Si cap/SiGe gate stacked-transistors. Through a careful analysis of the interface quality (interface states and roughness), we demonstrate that an ultrathin silicon cap is mandatory to obtain high hole mobility enhancement. Based on quantum mechanical simulations and capacitance-voltage characterization, we show that this silicon cap is not contributing any silicon parasitic channel conduction and degrades by only 1 /spl Aring/ the electrical oxide thickness in inversion. Due to this interface optimization, Si/sub 0.72/Ge/sub 0.28/ pMOSFETs exhibit a 58% higher mobility at high effective field (1 MV/cm) than the universal SiO/sub 2//Si reference and a 90% higher mobility than the HfO/sub 2//Si reference. This represents one of the best hole mobility results at 1 MV/cm ever reported with a high-/spl kappa//metal gate stack. We thus validate a possible solution to drastically improve the hole mobility in Si MOSFETs with high-/spl kappa/ gate dielectrics.

Novel 3D integration process for highly scalable Nano-Beam stacked-channels GAA (NBG) FinFETs with HfO2/TiN gate stack

Three- and four-level matrices of 15 times 70 nm Si Nano-Beams have been integrated with a novel CMOS gate-all-around process (GAA) down to 80 nm gate length. Thanks to this 3D-GAA extension of a Finfet process, a more than 5times higher current density per layout surface is achieved compared to planar transistors with the same gate stack (HfO 2/TiN/Poly-Si). For the first time, several properties of this novel 3D architecture are explored: (i) HfO2/TiN gate stack is integrated, (ii) electrons and holes mobilities are measured on 150 beams matrices (3 levels) and compared to those of planar transistors (hi) a sub-100nm channel width is demonstrated and (iv) specific 3D integration challenges like zipping between nano-beams are discussed

Novel integration process and performances analysis of Low STandby Power (LSTP) 3D multi-channel CMOSFET (MCFET) on SOI with metal / high-K gate stack

For the first time, ultra low I_OFF (16.5 pA/mum) and high I_ONN,P (2.27 mA/mum and 1.32 mA/mum) currents are obtained with a multi-channel CMOSFET (MCFET) architecture on SOI with a metal/high-K gate stack. This leads to the best I_ON/I_OFF ratios ever reported: 1.4 times 10⁸ (0.8 times 10⁸) for 50 nm n- (p-) MCFETs. We show, based on specifically developed integration process, characterization methods and analytical modeling, how those performances are obtained thanks to specific 3D MCFET features, in particular, transport properties, saturation regime and electrostatic behavior.

Simplified 0.35-μm flash EEPROM process using high-temperature oxide (HTO) deposited by LPCVD as interpoly dielectrics and peripheral transistors gate oxide

A simplified flash EEPROM process was developed using high-temperature LPCVD oxide both as flash cells interpoly dielectrics and as peripheral transistors gate oxide (decoding logic). An O/sub 2/ anneal at 850/spl deg/C lowers charge trapping and interface trap density induced by Fowler-Nordheim injection. However, electron trapping remains slightly higher than with dry thermal oxide. Similar memory charge loss and write-erase endurance are obtained as for ONO-insulated cells. HTO thus proves to have the required quality and reliability to be used in flash EEPROMs.