X. Garros

Insights on fundamental mechanisms impacting Ge metal oxide semiconductor capacitors with high-k/metal gate stacks

Capacitance-voltage (CV) measurements on germanium metal oxide semiconductor (MOS) structures show unusual frequency behavior compared to their silicon counterparts—a low-frequency behavior of the high-frequency CV characteristics is observed in the inversion regime, and the experimental CV curves in the depletion regime exhibit large features that have been attributed to high densities of interface defects (Dit). In this paper, an electrical model is proposed to give insights on the fundamental mechanisms impacting Ge structures from a careful analysis of these CV measurements. Thanks to this analytical model, both CV and GV (conductance-voltage) characteristics have been accurately simulated over a large range of gate voltages and frequencies. The modeling of the strong inversion regime confirms that the generation-recombination of minority carriers is assisted by bulk traps and shows that a small level of impurities in Ge—in the 1015–1016percm3 range—can explain the frequency dispersion observed in the...

Large-Scale Time Characterization and Analysis of PBTI In HFO2/Metal Gate Stacks

Many electrical properties of metal/high-k gate stack are dominated by defects. These defects play an important role in reliability issues in particular positive bias temperature instabilities (PBTI). In this paper, we investigate PBTI with a time resolved measurement technique allowing a large-scale time characterization. This technique allows us to separate different mechanisms, namely fast and slow trapping, newly slow stress-generated traps and finally positive charges. We clearly evidence which of them are or are not activated by temperature. We explain how to take into account these mechanisms for a precise lifetime extrapolation

Guidelines to improve mobility performances and BTI reliability of advanced high-k/metal gate stacks

A systematic study of mobility performances and BTI reliability was done in advanced dielectrics stacks. By reducing the oxide films thicknesses THKles2.5 nm, PBTI becomes generally very low and associated lifetimes are always over 10 years. By studying a large variety of dielectric stacks we also clearly demonstrate that mobility performances, interface defects Nit and NBTI reliability are strongly correlated. All are affected by nitrogen species N which is clearly identified as the main mobility killer when it reaches unintentionally the Si interface during the deposition of nitrided gates or the nitridation steps. However, by optimizing the gate stacks, excellent mobility performances, up to 100% universal mobility at Eeff=1 MV/cm, and reliability can be achieved.

20nm gate length trigate pFETs on strained SGOI for high performance CMOS

We present the shortest and narrowest high-κ/metal gate n- and pFETs on compressively strained enriched SiGe On Insulator (c-SGOI) reported to date (L<inf>G</inf>=20nm; W=30nm; T<inf>SiGe</inf>=15nm). The range of active area widths in this work allows observing the transition from biaxial to uniaxial stress due to lateral elastic strain relaxation, and its benefit down to 20nm gate length on hole mobility and pFET performance (up to ×2.85 I<inf>Dlin</inf> enhancement vs. SOI, I<inf>ON</inf>=520µA/µm / I<inf>OFF</inf>=130nA/µm at L<inf>G</inf>=20nm and V<inf>DS</inf>=−1V). Moreover, an improved electrostatic integrity compared to SOI pFETs is demonstrated in c-SGOI (DIBL=120mV/V vs. 160mV/V, respectively at L<inf>G</inf>=30nm). Combined to the intrinsic |V<inf>th,p</inf>| lowering properties of c-SiGe, these characteristics qualify trigate c-SGOI as a very promising candidate for high performance pMOSFETs.

In Depth Analysis of VT Instabilities in HFO2 Technologies by Charge Pumping Measurements and Electrical Modeling

This paper investigates VT instabilities in HfO2 /TiN stacks from CP measurements and electrical modeling. CP measurements are well correlated to pulsed Idvg measurements and can be easily used to obtain the Vt instability over a large scale of time from 0.1mus to fews seconds. A complete modeling of the CP and the pulsed Id Vg measurements has been done to localize spatially and energetically the traps in HfO2. The main band of defects responsible for Vt instabilities was found at ~0.9eV from the HfO2 conduction band but deep energy levels were also identified. The impact of the detrapping phenomena on CP measurements has been finally investigated. No influence of detrapping of electrons into the gate was found. And the detrapping into the substrate during the half of the ac cycle at Vg=-1.5V is almost complete for the traps filled at low Vg

Impact of dynamic variability on SRAM functionality and performance in nano-scaled CMOS technologies

In this paper we demonstrate that fast oxide trapping mechanism can be responsible for significant dynamic variability of Vt, gm and Id at circuit operating conditions. An estimation of the effect of these variabilities has been made using Monte Carlo simulations. The impact of the measured variabilities on SRAM performance is found appreciable since a margin of ~50mV in the minimum supply voltages is required to overcome this effect.

Impact of Single Charge Trapping on the Variability of Ultrascaled Planar and Trigate FDSOI MOSFETs: Experiment Versus Simulation

The impact of single charge trapping on the threshold voltage Vt of ultrascaled fully depleted silicon-on-insulator transistors is investigated through dynamic variability measurements and 3-D electrostatic simulations. In these undoped Si channel devices, Vt shifts induced by individual trapping events are exponentially distributed with distribution tail similarly as in BULK devices. This typical dependence is explained by the high sensitivity of Vt -with a bell-like shape-on the position of the trap over the channel. The tail, on the other hand, is attributed to defects in the buried oxide. Finally, device scaling is showed to increase dynamic Vt variability. In particular, the impact of a single charge on Vt is found to scale with the inverse of the device area.

High performance 70nm gate length Germanium-On-Insulator pMOSFET with high- /metal gate

We demonstrate for the first time 70 nm gate length TiN/HfO₂ pMOSFETs on 200 mm GeOI wafers, with excellent performances: I_ON=330 muA/mum & I_OFF=1 muA/mum @ V_d=-1.2 V (without germanide). These performances are obtained using adapted counterdoping and pocket implants. We report the best CV/I vs. I_OFF trade-off for Ge or GeOI: CV/I=4.4 ps, I_OFF=500 nA/mum @ V_d=-1 V. Moreover, based on fine electrical characterizations (mu, D_it, R_access) at T=77-300 K, in-depth analysis of both ON & OFF states were carried out. Besides, calibrated TCAD simulations were performed to predict the performance enhancements which can be theoretically reached after further device optimization. By using germanide and reducing both interface state density and diode leakage we expect I_ON=450 muA/mum, IOFF=100 nA/mum @ V_d=-1 V for L_g=70 nm.

High-k/metal Gate GeOI pMOSFET: Validation of the Lim&Fossum model for interface trap density extraction

The extraction of the trap density on Ge/gate-stack (top) and Ge/BOX (bottom) interfaces of germanium-on-insulator pMOSFETs is shown using the Lim & Fossum model historically developed for fully depleted SOI devices. The doping and the thickness of the Ge film do not change significantly the top interface trap density. The bottom one is slightly raised by doping the Ge film. This method can be used as a simple and efficient meaning of the interface trap density levels monitoring during process optimization of GeOI devices.

Modeling the Dynamic Variability Induced by Charged Traps in a Bilayer Gate Oxide

In this paper, we revisit the classic single layer defect centric model (DCM), largely used in reliability studies, in the more realistic case of bilayer gate oxide transistors integrating an interface layer and a high-K dielectric. The Monte Carlo method and 3-D electrostatic simulations are used to determine the impact of the traps present in both layers on the Vt of transistors. It is proved that the DCM is able to capture the trap-induced variability of bilayer transistors but with effective model parameters, which have no more a true physical meaning as in the case of the single layer gate oxide. An extended DCM, accounting for a two trap distributions, is then proposed to better explain the degradation measured on bilayer transistors. Finally, this extended DCM finds another application in the evaluation of the bias temperature instability-induced variability of static RAM cells.