C. P. Parry

Growth temperature dependence for the formation of vacancy clusters in Si/Si0.64Ge0.36/Si structures

The incorporation of vacancy clusters and vacancy point defects during the growth of Si/Si0.64Ge0.36/Si structures has been observed for growth temperatures between 250 °C and 550 °C using positron annihilation spectroscopy. A strong correlation between the electrical characteristics of the structures and the size and concentration of the clusters is observed. For the onset of two-dimensional hole gas behavior, a defect concentration less than 5×1016 cm−3 is required. A further reduction in concentration below 1×1016 cm−3 results in optimum electrical performance. The depth at which defects are observed increases with decreasing growth temperature indicating defect mobility during growth or subsequent annealing.

Elemental boron doping behavior in silicon molecular beam epitaxy

Boron-doped Si epilayers were grown by molecular beam epitaxy (MBE) using an elemental boron source, at levels up to 2×1020 cm−3, to elucidate profile control and electrical activation over the growth temperature range 450–900 °C. Precipitation and surface segregation effects were observed at doping levels of 2×1020 cm−3 for growth temperatures above 600 °C. At growth temperatures below 600 °C, excellent profile control was achieved with complete electrical activation at concentrations of 2×1020 cm−3, corresponding to the optimal MBE growth conditions for a range of Si/SixGe1−x heterostructures.

Temperature dependence of incorporation processes during heavy boron doping in silicon molecular beam epitaxy

Boron doped layers were grown by silicon molecular beam epitaxy to establish incorporation processes at temperatures between 900 and 450 °C. For temperatures exceeding 650 °C a surface accumulated phase of boron was formed when doping levels exceeded solid solubility limits. The properties of this surface phase were used to determine solubility limits for boron in silicon. Above 750 °C, the measured equilibrium solubility limit was in the 1019‐cm−3 range in good agreement with previously published annealing data and showing a gradual decrease with decreasing temperature. Below 650 °C, the processes leading to the formation of the surface phase were kinetically limited, manifested by a sharp increase in boron solubility limit, with completely activated levels above 1 × 1020 cm−3 realized. At intermediate growth temperatures the degree of dopant activation was found to be dependent on growth rate. The stability of fully activated highly‐doped boron layers, grown at low temperatures, to ex situ annealing is ...

Technique for producing highly planar Si/SiO0.64Ge0.36/Si metal–oxide–semiconductor field effect transistor channels

Si/Si0.64Ge0.36/Si heterostructures have been grown at low temperature (450 °C) to avoid the strain-induced roughening observed for growth temperatures of 550 °C and above. The electrical properties of these structures are poor, and thought to be associated with grown-in point defects as indicated in positron annihilation spectroscopy. However, after an in situ annealing procedure (800 °C for 30 min) the electrical properties dramatically improve, giving an optimum 4 K mobility of 2500 cm2 V – 1 s – 1 for a sheet density of 6.2 × 1011 cm – 2. The low temperature growth yields highly planar interfaces, which are maintained after anneal as evidenced from transmission electron microscopy. This and secondary ion mass spectroscopy measurements demonstrate that the metastably strained alloy layer can endure the in situ anneal procedure necessary for enhanced electrical properties. Further studies have shown that the layers can also withstand a 120 min thermal oxidation at 800 °C, commensurate with metal–oxide–semiconductor device fabrication.

Contamination issues during atomic hydrogen surfactant mediated Si MBE

We report an investigation into sources of contamination observed from a discharge type atomic hydrogen source during atomic hydrogen surfactant mediated growth. Secondary ion mass spectrometry (SIMS) has shown that the use of a PBN discharge cell within the source can lead to boron contamination. The concentration of boron contamination is found to depend on the hydrogen coverage and is electrically active. The alternative use of a quartz cell leads to significant oxygen contamination. The results of this study are applicable not only to the use of such sources during surfactant mediated growth but may have wide implications for their use during in situ cleaning of substrate surfaces.

ISSUES ON THE MOLECULAR-BEAM EPITAXIAL GROWTH OF P-SIGE INVERTED-MODULATION-DOPED STRUCTURES

The influence of boron segregation and silicon cap-layer thickness on two-dimensional hole gases (2-DHGs) has been investigated in Si/Si0.8Ge0.2/Si inverted-modulation-doped heterostructures grown by solid-source molecular-beam epitaxy. Boron segregation, which is significant in structures with small spacer layers, can be suppressed by growth interruption after the boron doping. How growth interruption affected the electrical properties of the 2-DHG and the boron doping profile as measured by secondary ion mass spectroscopy are reported. We report also on the role played by the unpassivated silicon cap, and compare carrier transport at the normal and inverted interfaces.

Elemental boron and antimony doping of MBE Si and SiGe structures grown at temperatures below 600°C

Abstract This paper considers the low temperature doping of (100) Si and SiGe structures with elemental B and Sb sources particularly with regard to obtaining very narrow delta doping spikes. B is found to be an excellent dopant at SiGe growth temperatures incorporating in an active state at concentrations up to 10%. B delta layers of 1 nm or less have also been grown. Sb is also shown to be capable of providing delta doped layers less than 2 nm wide. The B deltalayers have been incorporated into modulation doped structures yielding an order of magnitude increase in mobility at 77 K.

Ultrahigh room-temperature hole mobility in a SiGe quantum well

We report an ultrahigh room-temperature hole drift mobility obtained in a Si0.2Ge0.8 quantum well with a parabolic-like Ge profile, which has at its core a p-type modulation-doped (MOD) Si∕Si0.2Ge0.8∕Si0.65Ge0.35∕Si(001) heterostructure. High-conductivity holes at 293 K with a drift mobility of 3600cm2V−1s−1 at a sheet carrier density of 4.94×1012cm−2 were obtained in the Si0.2Ge0.8 quantum well after optimum annealing at 750 °C for 30 min. Hall mobility and sheet carrier density of this heterostructure are 1776cm2V−1s−1 and 2.37×1013cm−2, respectively. Structural characterization of the as-grown and the annealed samples revealed that the annealing had caused Si0.2Ge0.8 channel broadening, smearing of interfaces, and formation of a parabolic-like Ge profile that significantly improved room-temperature hole transport properties. The reported values of hole mobility are much higher than in the bulk Ge.

Structural and electrical properties of p+n junctions in Si by low energy Ga+ implantation

Ultrashallow p+n junctions have been formed in silicon by low energy (5.5 keV) Ga+ implantation into n-type substrates. This avoids the use implantation of molecular species such as BF2+ or preamorphization with Ge+ or Si+, which degrade the integrity of p+n junctions in metastably strained SixGe1−x layers. High resolution secondary ion mass spectroscopy measurements indicate an implant peak at less than 10 nm, except for postanneal temperatures above 800 °C, for which severe loss of profile control was observed. Electrical characteristics of the implanted junctions were determined from diode current–voltage measurements and Hall data. At low anneal temperatures, these showed good rectification behavior, with an ideality factor of 1.1±0.1 and a reverse bias leakage of ≈3 μA cm−2 in a relatively large junction area of 5×10−2 cm2. The electrical properties of the p+n junctions were found to be sensitive to implant dose, improving with increasing dose. At 580 °C, implant doses were achieved that were complet...

SiGe CMOS fabrication using SiGe MBE and anodic/LTO gate oxide

An investigation of an SiGe CMOS process fulfilling low-thermal-budget requirements was carried out. Three different undoped layers were grown successively by MBE: a 20 nm buffer layer, a 15 nm SiGe layer and a 15 nm cap layer. The Ge concentration of the SiGe layer was either uniform 20% or linearly graded 0-40% from the substrate to the surface. A 50 nm thick undoped Si layer was grown for the reference devices. Anodic oxide and LTO were used as gate dielectrics. The annealing was performed at relatively modest temperatures. The SiGe p-MOSFETs were compared to the Si reference devices. We report an enhancement of the hole mobility up to 70% for the SiGe p-MOSFETs.