T E Whall

High conductance Ge p-channel heterostructures realized by hybrid epitaxial growth

Strained Ge p-channel heterostructures have been realized by hybrid-epitaxial growth. Strain-tuning Si0.4Ge0.6 virtual substrates were grown by ultra-high vacuum chemical vapour deposition and active layers were deposited by solid-source molecular beam epitaxy at low temperature. Following ex situ annealing, Hall effect measurements revealed a hole mobility of 1900 cm2 V−1 s−1 at 300 K (27 000 cm2 V−1 s−1 at 10 K), with a density of 1.8 × 1012 cm−2, giving a conductance in excess of current Ge heterostructures. Using a maximum-entropy mobility-spectrum analysis, 1.0 × 1012 cm−2 of these holes were found to have a mobility of 2700 cm2 V−1 s−1 at 300 K.

Indication of velocity overshoot in strained Si0.8Ge0.2 p-channel MOSFETs

A velocity-field study of several Si0.8Ge0.2/Si p-channel MOSFETs with self-aligned poly-Si gates, thick gate oxides and effective channel lengths ranging from 1.5 to 8.5 µm, was carried out at room temperature. Comprehensive two-dimensional simulations of devices using drift-diffusion (DD), and bulk Monte Carlo calibrated hydrodynamic (HD) and energy transport (ET) models have revealed enhanced high-field hole transport in strained-channel MOSFETs. A close agreement is obtained between higher-level (HD/ET) models and DD model with calibrated high-field mobility parameters. It is found that the relatively low value of extracted saturation velocity in long-channel Si0.8Ge0.2 p-MOSFETs increases considerably as the gate length is decreased. The increase in short-channel samples is attributed to non-equilibrium transport effects in the region near the source, resulting from higher mobility and longer relaxation times of holes in the strained SiGe layer. Our results not only confirm the expected advantage of strained SiGe p-MOSFETs in low-field transport, but also indicate that this is accompanied by an early onset of velocity overshoot, which may be beneficial in aggressively scaled devices.

Contamination issues during atomic hydrogen surfactant mediated Si MBE

We report an investigation into sources of contamination observed from a discharge type atomic hydrogen source during atomic hydrogen surfactant mediated growth. Secondary ion mass spectrometry (SIMS) has shown that the use of a PBN discharge cell within the source can lead to boron contamination. The concentration of boron contamination is found to depend on the hydrogen coverage and is electrically active. The alternative use of a quartz cell leads to significant oxygen contamination. The results of this study are applicable not only to the use of such sources during surfactant mediated growth but may have wide implications for their use during in situ cleaning of substrate surfaces.

SiGe CMOS fabrication using SiGe MBE and anodic/LTO gate oxide

An investigation of an SiGe CMOS process fulfilling low-thermal-budget requirements was carried out. Three different undoped layers were grown successively by MBE: a 20 nm buffer layer, a 15 nm SiGe layer and a 15 nm cap layer. The Ge concentration of the SiGe layer was either uniform 20% or linearly graded 0-40% from the substrate to the surface. A 50 nm thick undoped Si layer was grown for the reference devices. Anodic oxide and LTO were used as gate dielectrics. The annealing was performed at relatively modest temperatures. The SiGe p-MOSFETs were compared to the Si reference devices. We report an enhancement of the hole mobility up to 70% for the SiGe p-MOSFETs.

Study of velocity field characteristics in pseudomorphic Si 0.8 Ge 0.2> p-channel metal-oxide-semiconductor field effect transistor

Abstract In this work we report on the enhanced mobility and high electric field characteristics of SiGe p-channel MOSFETs. In the low electric field regime, the devices exhibit effective mobility three times greater than comparable standard Si devices. To determine accurate hole transport characteristics, an analytical modelling of these devices is implemented that takes into account the source drain resistance and short channel effects.

Impact ionization in strained Si devices

Impact ionization in biaxial tensile strained Si n and p metal-oxide-semiconductor field-effect transistors is investigated. Despite the smaller band gap and higher carrier mobility in strained Si, no evidence for significantly increased impact ionization is found. This is attributed to the reduced density of states in strained Si, brought about by strain-induced band splitting, limiting the opportunities for scattering.

Halo implant in pseudomorphic SiGe channel p-MOSFET devices to reduce short channel effect

Halo ion implantation was adopted to reduce the short channel effect (SCE) of a buried channel p-MOSFET device on pseudomorphic Si0.70Ge0.30 layers. The strained pseudomorphic Si0.70Ge0.30 layer of 10 nm thickness, with a Si cap layer on top, was grown using molecular beam epitaxy. The results show an overall reduction in threshold voltage (Vth) roll-off in both Si and pseudomorphic SiGe devices. Halo implantation of As+, 120 keV and dose 2 × 1013 cm−2, was successfully used to reduce roll-off for the 2 nm Si cap SiGe device by 0.3 V. However, it was found that halo implantation causes the reverse short channel effect (RSCE) on the devices, which can result in Vth roll-up with reducing channel length. The effect of the RSCE becomes greater with increasing Si cap thicknesses of the SiGe devices. Also, non-halo implanted devices were found to demonstrate the RSCE. This is due to excess interstitials from the source/drain implant and their subsequent diffusion, which causes virtual halo dopant to form in non-halo implanted devices.

A TEM study of Ge-on-(111)Si structures for potential use in high performance PMOS device technology

We have performed a transmission electron microscopical study of samples where pure Ge has been grown on differently oriented Si wafers by reduced pressure chemical vapour deposition. In the present study we examine pure Ge layers grown on (111)Si wafers by annular dark-field (ADF) scanning transmission electron microscopy (STEM) and by high-resolution electron microscopy (HREM). There is evidence of immediate strain relaxation taking place by dislocations and twinning. A novel configuration of micro-twins has been observed at the interface between the pure Ge and the underlying (111)Si wafer. Growth mechanisms and models to explain the interfacial configurations of this type of wafer are suggested.

Dynamic threshold mode operation of p-channel Si and strained-SiGe MOSFETs between 10 K and 300 K

An investigation of dynamic-threshold (DT) performance was carried out on a 0.5 µm gate length p-type Si:SiGe heterostructure field effect transistor, for temperatures ranging from T = 300 K to T = 10 K. The maximum low-field transconductance of DT-mode operation was found to be 30% higher than in normal mode, through a better control of carriers in the channel. The subthreshold slope of the device, when operated in DT mode, also improved, decreasing by 28%. The sensitivity of the threshold voltage to substrate bias was extracted from experimental data over the whole temperature range, and was found to be higher in the SiGe device than in a corresponding Si control device. The substrate sensitivity was used together with equations derived from classical Si MOSFET theory to successfully predict the performance improvement due to DT-mode operation, at all temperatures.

Hot Carrier Transport in SiGe/Si Two-Dimensional Hole Gases

The hot carrier energy loss rate in a two dimensional hole gas in compressively strained SiGe quantum wells has been studied for samples with a Ge content (x= 0.2) and carrier concentrations ranging from 3x1011 to 7x1011cm−2. The energy loss in this highly non-parabolic system is dominated by acoustic phonon deformation potential scattering, whereas the piezoelectric interaction is negligible.