C. Parker

Ultrathin oxide-nitride gate dielectric MOSFET's

The first ultrathin oxide-nitride (O-N) gate dielectrics with oxide equivalent thickness of less than 2 nm have been deposited and characterized in n-MOSFETs. The O-N gates, deposited by remote plasma-enhanced CVD, demonstrate reduced gate leakage when compared with oxides of equivalent thickness while retaining comparable drive currents.

Effect of polysilicon gate type on the flatband voltage shift for ultrathin oxide-nitride gate stacks

In this work, we demonstrate that the magnitude of flatband voltage (V/sub FB/) shift for ultrathin (<2 nm) silicon dioxide-silicon nitride (ON) gate stacks in MOSFETs depends on the Fermi level position in the gate material. In addition, a fixed positive charge at the oxide-nitride interface was observed.

Reliability of nitrided Si–SiO2 interfaces formed by a new, low‐temperature, remote‐plasma process

Controlled amounts of nitrogen atoms have been incorporated at Si–SiO2 interfaces by a new, low‐temperature (300 °C), remote‐plasma process, and corresponding improvements in device reliability are reported. Interfacial nitrogen‐atom concentrations, up to 1×1015 cm−2, were obtained by a predeposition, remote plasma‐assisted oxidation using mixtures of N2O and O2. Auger electron spectroscopy and secondary ion mass spectrometry studies to analyze N‐atom concentrations at Si–SiO2 interfaces are discussed. Also, the results of electrical testing of submicron, n‐channel metal–oxide–silicon field‐effect transistors fabricated with this new process technology are reported. We found that the incorporation of N atoms at the Si–SiO2 interface increased current drive capability at high gate voltages but did not affect the threshold voltage of devices or the peak channel transconductance, gm. Device reliability, as measured by resistance to peak gm degradation after hot‐carrier stressing, was found to increase with i...

Monolayer Nitrogen-Atom Distributions in Ultrathin Gate Dielectrics by Low-Temperature Low-Thermal-Budget Processing.

The research reported in this paper is based on an approach to low-temperature/low-thermal budget device fabrication that combines plasma and rapid thermal processing, and which has been customized to control separately i) the N-atom bonding chemistry and composition profiles, and ii) the structural and chemical relaxations in stacked gate structures. Control of N-atom incorporation at the monolayer level at the crystalline- and polycrystalline-Si interfaces, and at alloy levels within the bulk dielectrics has been achieved by combining low-temperature (~300° C) plasma-assisted processes to generate the N-atom concentration profiles, with low-thermal-budget rapid thermal annealing (RTA) to promote chemical and structural relaxations that minimize defects and defect precursors. Device measurements indicate that N-atom incorporation improves reliability with respect to hot carrier degradation of field effect transistors.

Controlled nitrogen incorporation at Si-SiO 2 interfaces and in thin gate dielectrics by remote-plasma-assisted oxidation and deposition processes

Abstract Low-temperature, 300°C, plasma processes are described for controlled incorporation of N at SiSiO 2 interfaces, and in thin gate dielectrics. N incorporation at mono- and sub-monolayer levels have been achieved at SiSiO 2 interfaces by plasma-assisted oxidation in N 2 O and N 2 O O 2 mixtures. N incorporation in stacked dielectrics with Si oxynitride or nitride layers has been demonstrated by remote plasma enhanced chemical-vapor deposition (PECVD).

Controlled Nitrogen-Atom Incorporation At Si-SiO2 Interfaces in Mis Devices

We have developed a new pre-deposition, remote N 2 O plasma oxidation treatment for forming nitrided SiO 2 films and report here the quality and reliability of devices fabricated with these films. The Si-dielectric heterostructure process has been separated into three independently-controlled steps: i) final Si surface cleaning, and Si – SiO 2 interface formation by plasma-assisted oxidation/nitridation at 300 °C; ii) remote plasma-enhanced chemical vapor deposition of nitrided dielectrics, also at 300 °C; and iii) optional post-deposition rapid thermal annealing. This paper focuses on the first step in which the oxidation has been performed with O 2 , N 2 O or N 2 O / O 2 mixtures to control the amount of N-atoms at the interface, N int . We show that the incorporation of up to ∼ 10 15 N-atoms/cm 2 at the Si-SiO 2 interface by this process has no effect on threshold voltage, V t , or peak channel transconductance, g m,max , but does improve high-field g m and transistor drive current. Improved resistance to V t and g m,max degradation during hot-carrier stressing of sub-micron devices is also discussed.

Evaluation and Comparison of 3.0 nm Gate-Stack Dielectrics for Tenth-Micron Technology NMOSFETs

As device dimensions continue to scale down into the deep submicrometer regime, there is an increasing challenge for fabricating robust gate dielectrics with low susceptibility to process-induced device degradation and a continuous motivation for the exploration of new options for thin gate dielectrics. This work assesses a variety of gate stack processing techniques as alternatives to conventionally furnace grown gate oxides in the context of a tenth-micron technology, which features LOCOS isolated, two-implant channel, NMOS transistors fabricated with a 3.0 nm thick gate dielectric, 0.15 μm thick polysilicon gate, implanted extension- and contact-junctions of 20 and 50 nm deep, respectively, and effective channel lengths down to 0.12 μm, operating at 1.2 volts. The alternative deposition and oxidation techniques include furnace oxynitride formation, rapid-thermal oxidation (RTO), rapid-thermal chemical vapor deposition (RTCVD) and plasma-assisted chemical vapor deposition (RPECVD). Compared to the 0.25- and 0.18-μm technological nodes, the thermal budgets associated with gate oxide formation are dramatically lower and their impact on channel dopant redistribution is not as strong as in previous technologies. Negligible polysilicon depletion effects were observed in the fabricated devices (C inv /C ox = 97%). Drive currents and threshold voltage control comparable to furnace oxides were achieved by alternative gate-stack processing techniques.

High power nitrogen-incorporating remote plasma oxidation process for MOS applications

Summary form only given. A 400 W remote plasma oxidation process has been developed in a cluster tool which uses N/sub 2/O and O/sub 2/ for controlling incorporated amounts of nitrogen within the grown oxide. This technique has been developed for Si/SiO/sub 2/ interface formation for addition of nitrogen at the interface. Verification through in-situ Auger electron spectroscopy demonstrates that nitrogen is incorporated within the 15 /spl Aring/ grown oxide and is therefore confined to the Si/SiO/sub 2/ interface. Ex-situ SIMS analysis indicates incorporation of /spl sim/8/spl times/10/sup 14/ atoms/cm/sup 2/ of nitrogen at the interface for a 30 second oxidation in pure N/sub 2/O, and the nitrogen content can be effectively controlled by adding O/sub 2/ to the process mixture and varying the N/sub 2/O/O/sub 2/ percentage. Gate stacks for MOS devices are fabricated by depositing a bulk oxide by remote plasma enhanced CVD (RPECVD) on top of the grown interface and then capping the structure with rapid thermally deposited polysilicon. MOSFET devices demonstrate the usefulness of this oxidation technique for interface formation.

Incorporation of Nitrogen Atoms at Si/SiO 2 Interfaces of Field Effect Transistors (FETs) to Improve Device Reliability

Incorporation of N-atoms at the Si-Si02 interface in field effect transistors, FETs, with ultrathin dielectrics (≤ 5.5 nm) improves device reliability. Four aspects of our recent research on nitrided Si-Si02 interfaces are discussed in this paper: i) the low-temperature/low-thermal budget process by which interface chemistry is controlled, and optimized; ii) the use of on-line and off-line diagnostics to determine the spatial confinement and concentration of interfacial N-atom incorporation; iii) comparisons of device properties for non-nitrided and nitrided interfaces; and iv) the proposal of an atom-scale model for the role that interfacial N-atoms play in improving device reliability.