Sunil V. Hattangady

CMOS metal replacement gate transistors using tantalum pentoxide gate insulator

This paper reports a full CMOS process using a combination of a TiN/W Metal Replacement Gate Transistor design with a high dielectric constant gate insulator of tantalum pentoxide over thin remote plasma nitrided gate oxide. MOS devices with high gate capacitances equivalent to that for <2 nm SiO/sub 2/ but having relatively low gate leakage are reported. Transistors with gate lengths near or below 0.1 /spl mu/m have good characteristics. Working CMOS circuits using Ta/sub 2/O/sub 5/ gate insulator are demonstrated for the first time.

Low voltage stress-induced-leakage-current in ultrathin gate oxides

Stress-induced-leakage-current (SILC) is an important concern in ultrathin gate oxides because it may impose constraints on dielectric thickness scaling. We show that for oxides less than /spl sim/3.5 nm thick, interfacial traps generated from direct tunneling stress result in a sense voltage dependent SILC mechanism that can dominate the gate leakage current at low operating voltages.

Sub-100 nm gate length metal gate NMOS transistors fabricated by a replacement gate process

A novel replacement gate design with 1.5-3 nm oxide or remote plasma nitrided oxide gate insulators for sub-100 nm Al/TiN or W/TiN metal gate nMOSFETs is demonstrated. The source/drain regions are self-aligned to a poly gate which is later replaced by the metal gate. This allows the temperatures after metal gate definition to be limited to 450/spl deg/C. Compared to pure SiO/sub 2/, the nitrided oxides provide increased capacitance with less penalty in increased gate current. A saturation transconductance (g/sub m/) of 1000 mS/mm is obtained for L/sub gate/=70 nm and t/sub OX/=1.5 nm. Peak cutoff frequency (f/sub T/) of 120 GHz and a low minimum noise figure (NF/sub min/) of 0.5 dB with associated gain of 19 dB are obtained for t/sub OX/=2 nm and L/sub gate/=80 nm.

Physical oxide thickness extraction and verification using quantum mechanical simulation

Physical gate oxide thickness is extracted from TiN gate PMOS and NMOS capacitance voltage measurements using an efficient multi-band Hartree self-consistent Poisson solver. The extracted oxide thicknesses are then used to perform direct tunneling current simulations. Excellent agreement between measured a simulated tunnel current is obtained without the use of adjustable fitting parameters.

Feasibility of using W/TiN as metal gate for conventional 0.13 /spl mu/m CMOS technology and beyond

We demonstrate the feasibility of using W/TiN as metal-gate on thin gate dielectrics (/spl les/33 /spl Aring/) and with high temperature (>950/spl deg/C) S/D annealing for 0.13 /spl mu/m CMOS applications. Close to ideal C-V characteristics are obtained indicating good Si/SiO/sub 2/ interface quality and free from gate depletion. The gate sheet resistance is about 2 ohm//spl square/, nearly constant down to 0.05 /spl mu/m. Under fixed effective fields, the electron and hole mobility are comparable to or slightly better than those of poly gate devices. Compared to poly gate devices, the W/TiN on 33 /spl Aring/ pure oxide has inferior charge-to-breakdown (Q/sub bd/) distribution under substrate (+V/sub G/) injection. However, a remote-plasma nitrided oxide (RPNO) can greatly improve the +V/sub G/ Q/sub bd/ distribution for the W/TiN case. Short-channel W/TiN pMOS transistors are fabricated with excellent characteristics down to L/sub gate//spl ap/0.07 /spl mu/m. For nMOS under +V/sub G/ direct tunneling (DT) or Fowler-Nordheim (F-N) tunneling injection with S/D grounded, the W/TiN device has a higher substrate hole current density (J/sub p/) than n/sup +/ poly-gate device (by about an order magnitude larger). This higher J/sub p/ is believed due to the tunneling of valence-band electron and thus has no impact on the thin (t/sub ox//spl les/33 /spl Aring/) gate oxide reliability.

Ultrathin nitrogen-profile engineered gate dielectric films

A simple and novel scheme is presented for the formation of /spl sim/4 nm gate dielectric films with nitrogen at the top (gate electrode/dielectric) interface. It consists of low-temperature, remote, high-density N/sub 2/-plasma nitridation of thermal SiO/sub 2/, followed by a post-nitridation anneal. The key results are: (a) high N concentrations (10-20 at.%) incorporated uniformly within /spl sim/0.7 nm of the oxide surface, (b) little V/sub fb/-shift and no significant variation in midgap-D/sub it/ from that of control oxide, (c) suppression of B-penetration for high B levels and for high thermal budgets including a hydrogen ambient, and (d) no evidence of damage to the oxide.

Securing Mobile Appliances: New Challenges for the System Designer

As intelligent electronic systems pervade all aspects of our lives, capturing. storing, and communicating a wide range of sensitive and personal data, security is emerging as a critical concern that must be addressed in order to enable several current and future applications. Mobile appliances, which will play a critical role in enabling the visions of ubiquitous computing and communications, and ambient intelligence, are perhaps the most challenging to secure - they often rely on a public medium for (wireless) communications, are easily lost or stolen due to their small form factors and mobility, and are highly constrained in cost and size, as well as computing and battery resources. This paper presents an introduction to security concerns in mobile appliances, and translates them into challenges that confront system architects, HW engineers, and SW developers, including how to bridge the processing and battery gaps, efficient tamper-proofing of devices, content protection, etc. Recent innovations and emerging commercial technologies that address these issues are also highlighted. We envision that. for a large class of embedded systems, security considerations will pervade all aspects of system design, driving innovations in system architecture, software, circuits, and design methodologies.

A 0.10 /spl mu/m gate length CMOS technology with 30 /spl Aring/ gate dielectric for 1.0 V-1.5 V applications

High performance 0.1 /spl mu/m (physical) gate length CMOS with 30 /spl Aring/ gate dielectric (C-V: gate accumulated at V/sub gb/=-3 V) is demonstrated at 1.0 V-1.5 V. Scaling to 0.1 /spl mu/m L/sub gate/ CMOS is described. At 1.5 V, nMOS strong and nominal I/sub drive/=757 and 700 /spl mu/A//spl mu/m, and pMOS strong and nominal I/sub drive/=337 and 300 /spl mu/A//spl mu/m. For high performance at 1.0 V, n- and pMOS are designed with low V/sub T/ and higher I/sub off/ (100 nA//spl mu/m at L/sub g//sup min/). At 1 V, nMOS strong and nominal I/sub drive/ is 516 and 473 /spl mu/A//spl mu/m; pMOS strong and nominal I/sub drive/ is 220 and 188 /spl mu/A//spl mu/m. Benchmarking to FOM and CV/I metrics is performed for this 1.0-1.5 V, 0.1 /spl mu/m node and prior 1.8-1.5 V, 0.18 /spl mu/m nodes. Present 1.5 V, 0.1 /spl mu/m CMOS (as well as our recently reported 1.8-1.5 V, 0.18 /spl mu/m CMOS) has FOM and CV/I values better than the literature trend. The FOM at V/sub DD/=1.0 V (max I/sub off/=100 nA//spl mu/m) is the same as the 1.5 V FOM (max I/sub off/=1 nA//spl mu/m).

Extending the reliability scaling limit of SiO/sub 2/ through plasma nitridation

We demonstrate a manufacturable remote plasma nitridation process that significantly extends the reliability scaling limit of SiO/sub 2/ based gate dielectrics.

A comparison of TiN processes for CVD W/TiN gate electrode on 3 nm gate oxide

CVD W/CVD TiN stacks are studied for the first time as gate electrodes on 3 nm gate oxide and compared with the CVD W/PVD (sputtering) TiN gate stacks and the baseline n/sup +/ poly gate. It is found that the PVD TiN has higher metal-to-SiO/sub 2/ barrier height (/spl sim/3.77 eV) than that of the CVD TiN (3.62 eV). The CVD W/PVD TiN gates without high temperature (>900 C) RTP anneal show good electrical characteristics on 3 nm gate oxide, and the CVD TiN is less favorable due to its high impurities. High temperature anneal cause fluorine in CVD W to diffuse and interact with the gate oxide which adversely affect the gate oxide integrity (GOI). The remote plasma nitrided gate oxide (RPNO) provides a barrier between the TiN and gate oxide, and thus prevents or reduces the F-SiO/sub 2/ interaction, resulting in metal gate GOI comparable to that of poly gate. The CVD metal gate is a good candidate for the non-conventional, high aspect ratio grooved gate structures due to its good conformality.