J. J. Wortman

Modeling study of ultrathin gate oxides using direct tunneling current and capacitance-voltage measurements in MOS devices

Using both quantum mechanical calculations for the silicon substrate and a modified WKB approximation for the transmission probability, direct tunneling currents across ultra-thin gate oxides of MOS structures have been modeled for electrons from the inversion layers in p-type Si substrates. The modeled direct tunneling currents have been compared to experimental data obtained from nMOSFETs with direct tunnel gate oxides. Excellent agreement between the model and experimental data for gate oxides as thin as 1.5 nm has been achieved. Advanced capacitance-voltage techniques have been employed to complement direct tunneling current modeling and measurements. With capacitance-voltage (C-V) techniques, direct tunneling currents can be used as a sensitive characterization technique for direct tunnel gate oxides. The effects of both silicon substrate doping concentration and polysilicon doping concentration on the direct tunneling current have also been studied as a function of applied gate voltage.

Estimating oxide thickness of tunnel oxides down to 1.4 nm using conventional capacitance-voltage measurements on MOS capacitors

High-frequency capacitance-voltage (C-V) measurements have been made on ultrathin oxide metal-oxide-semiconductor (MOS) capacitors. The sensitivity of extracted oxide thickness to series resistance and gate leakage is demonstrated. Guidelines are outlined for reliable and accurate estimation of oxide thickness from C-V measurements for oxides down to 1.4 nm.

Modeled tunnel currents for high dielectric constant dielectrics

The effect of dielectric constant and barrier height on the WKB modeled tunnel currents of MOS capacitors with effective oxide thickness of 2.0 nm is described. We first present the WKB numerical model used to determine the tunneling currents. The results of this model indicate that alternative dielectrics with higher dielectric constants show lower tunneling currents than SiO/sub 2/ at expected operating voltages. The results of SiO/sub 2//alternative dielectric stacks indicate currents which are asymmetric with electric field direction. The tunneling current of these stacks at low biases decreases with decreasing SiO/sub 2/ thickness. Furthermore, as the dielectric constant of an insulator increased, the effect of a thin layer of SiO/sub 2/ on the current characteristics of the dielectric stack increases.

Optimization of the germanium preamorphization conditions for shallow-junction formation

Shallow p/sup +/-n and n/sup +/-p junctions were formed in germanium preamorphized Si substrates. Germanium implantation was carried out over the energy range of 50-125 keV and at doses from 3*10/sup 14/ to 1*10/sup 15/ cm/sup -2/. p/sup +/-n junctions were formed by 10-keV boron implantation at a dose of 1*10/sup 15/ cm/sup -2/. Arsenic was implanted at 50 keV at a dose of 5*10/sup 15/ cm/sup -2/ to form the n/sup +/-p junctions. Rapid thermal annealing was used for dopant activation and damage removal. Ge, B, and As distribution profiles were measured by secondary ion mass spectroscopy. Rutherford backscattering spectrometry was used to study the dependence of the amorphous layer formation on the energy and dose of germanium ion implantation. Cross-sectional transmission electron microscopy was used to study the residual defects formed due to preamorphization. Complete elimination of the residual end-of-range damage was achieved in samples preamorphized by 50-keV/1*10/sup 15/ cm/sup -2/ germanium implantation. Areal and peripheral leakage current densities of the junctions were studied as a function of germanium implantation parameters. The results show that high-quality p/sup +/-n and n/sup +/-p junctions can be formed in germanium preamorphized substrates if the preamorphization conditions are optimized. >

A comparative study of gate direct tunneling and drain leakage currents in n-MOSFET's with sub-2 nm gate oxides

This work examines different components of leakage current in scaled n-MOSFETs with ultrathin gate oxides (1.4-2.0 nm). Both gate direct tunneling and drain leakage currents are studied by theoretical modeling and experiments, and their effects on the drain current are investigated and compared. It concludes that the source and drain extension to the gate overlap regions have strong effects on device performance in terms of gate tunneling and off-state drain currents.

Residual defects following rapid thermal annealing of shallow boron and boron fluoride implants into preamorphized silicon

Shallow BF2 and B implants (42 keV, 2×1015 cm−2) were conducted at either liquid nitrogen or room temperature into deeply preamorphized (100) Si. Cross‐sectional transmission electron microscopy revealed that subsequent rapid thermal annealing (RTA) of the room‐temperature implanted BF2 sample in the temperature range 950–1150 °C for 10 s created three classes of secondary defects at three different depth levels. The depths corresponded closely to the projected range of the BF2 implant, the deep amorphous/crystalline interface, and the region immediately below the interface. In contrast, RTA of preamorphized Si with or without the shallow B implant both resulted in a high perfection surface region with secondary defects only in the region below the deep amorphous/crystalline interface. A phenomenological model for nucleation of the separate layers of defects is presented.

Transient enhanced diffusion during rapid thermal annealing of boron implanted silicon

Enhanced diffusion of ion implanted boron in silicon during the first few seconds (transient) of rapid thermal annealing (RTA) has previously tentatively been attributed to either interstitial boron diffusion or damage enhanced diffusion. We have performed various anneal sequences of 11B implanted Si combined with post‐implantation of 10B and measured the boron concentration profiles with secondary ion mass spectroscopy. The data show that the enhanced diffusion found in the tail of the profiles after RTA is not caused by fast diffusion of boron ending up at interstitial sites after the slowing down during implantation. Rather the enhanced diffusion in the tail is associated with the implantation damage annealing.

Rapid thermal annealing of arsenic and boron‐implanted silicon

Annealing of ion implantation damage and concomitant electrical activation of dopants, depth profiles, and lattice location of dopants have been studied in arsenic and boron‐implanted specimens after rapid thermal annealing. A ‘‘complete’’ annealing of displacement damage with full electrical activation of dopants and profile broadening less than 100 A can be attained for shallow implants whereas some extended defects are retained for deep implants. Mechanisms of rapid thermal annealing and its implications in solid state device fabrication are discussed.

Temperature uniformity in RTP furnaces

The heat transfer to a wafer in a rapid thermal processing (RTP) furnace is simulated by an analytical/numerical model. The model includes radiation heat transfer to the wafer from the lamps, heat conduction within the wafer, and emission of radiation from the wafer. Geometric optics are used to predict the radiant heat flux distribution over the wafer. The predicted wafer surface temperature distribution is compared to measurements made in an RTP furnace for two different reflector geometries. Lamp configurations and the resulting irradiance required to produce a uniform wafer temperature are defined. >

Formation of titanium and cobalt germanides on Si (100) using rapid thermal processing

Titanium and cobalt germanides have been formed on Si (100) substrates using rapid thermal processing. Germanium was deposited by rapid thermal chemical vapor deposition prior to metal evaporation. Solid phase reactions were then performed using rapid thermal annealing in either Ar or N2 ambients. Germanide formation has been found to occur in a manner similar to the formation of corresponding silicides. The sheet resistance was found to be dependent on annealing ambient (Ar or N2) for titanium germanide formation, but not for cobalt germanide formation. The resistivities of titanium and cobalt germanides were found to be 20 µΩ-cm and 35.3µΩ-cm, corresponding to TiGe2 and Co2Ge, respectively. During solid phase reactions of Ti with Ge, we have found that the Ti6Ge5 phase forms prior to TiGe2. The TiGe2 phase was found to form approximately at 800° C. Cobalt germanide formation was found to occur at relatively low temperatures (425° C); however, the stability of the material is poor at elevated temperatures.