C. Patrick Yue

Modeling of Mutual Coupling Between Planar Inductors in Wireless Power Applications

This paper presents a compact model of mutual inductance between two planar inductors, which is essential to design and optimize a wireless power transmission system. The tracks of the planar inductors are modeled as constant current carrying filaments, and the mutual inductance between individual filaments is determined by Neumanns integral. The proposed model is derived by solving Neumanns integral using a series expansion technique. This model can predict the mutual inductance at various axial and lateral displacements. Mutual coupling between planar inductors is computed by a 3-D electromagnetic (EM) solver, and the proposed model shows good agreement with these numerical results. Different types of planar inductors were fabricated on a printed circuit board (PCB) or silicon wafer. Using these inductors, wireless power links were constructed for applications like implantable biomedical devices and contactless battery charging systems. Mutual inductance was measured for each of the cases, and the comparison shows that the proposed model can predict mutual coupling suitably.

17.11 A 0.65ns-response-time 3.01ps FOM fully-integrated low-dropout regulator with full-spectrum power-supply-rejection for wideband communication systems

High performance low-dropout regulators (LDOs) are indispensable in a systemon-a-chip (SoC) due to their low output noise, fast transient response and good power supply rejection (PSR) characteristics. In general, differential analog circuit loads need an LDO with high PSR, digital circuit loads need an LDO with fast load transient response, while single-ended analog/RF circuit loads need an LDO with both high PSR and fast transient response. Figure 17.11.1 shows an LDO embedded in an optical receiver that helps improve the sensitivity of the front-end system. On-chip LDOs with PSR in the GHz range are in high demand for wideband optical communication systems because there is only one photo detector in the optical receiver and supply voltage variations would degrade its sensitivity severely.

Towards indoor localization using Visible Light Communication for consumer electronic devices

Indoor localization is the fundamental capability for indoor service robots and indoor applications on mobile devices. To realize that, the cost of sensors is of great concern. In order to decode the signal carried out by the LED beacons, we propose two reliable solutions using common sensors available on consumer electronic devices. Firstly, we introduce a dedicated analog sensor, which can be directly connected to the microphone input of a computer or a smart phone. It decodes both the signal pattern and signal strength of a beacon. Secondly, we utilize rolling-shutter cameras to decode the signal pattern, providing potential solutions to the localization of hand-held devices with cameras. In contrast to existing widely-applied indoor localization approaches, like vision-based and laser-based methods, our approach reveals its advantages as low-cost, globally consistent and it retains the potential applications using Visible Light Communication(VLC). We also study the characteristics of the proposed solutions under typical indoor conditions by experiments.

Design and Characterization of Wireless Power Links for Brain–Machine Interface Applications

In this paper, the design of an inductive power link (IPL) for wireless power transfer (WPT) in brain-machine interface (BMI) applications is thoroughly studied. The constraints and requirements of BMI applications are analyzed. By theoretical derivations, the relationships between the IPL performances and its electrical parameters are determined. The design guidelines for the IPL physical parameters are then obtained through experimental characterizations. Experimental results show that with proper IPL design, the efficiency can be improved from the previously reported values of 29.9% and 4.3% to 33.1% and 9.2% for BMI WPT distances of 5 and 12.5 mm, respectively.

Concurrent Design Analysis of High-Linearity SP10T Switch With 8.5 kV ESD Protection

This paper discusses concurrent design and analysis of the first 8.5 kV electrostatic discharge (ESD) protected single-pole ten-throw (SP10T) transmit/receive (T/R) switch for quad-band (0.85/0.9/1.8/1.9 GHz) GSM and multiple-band WCDMA smartphones. Implemented in a 0.18 μm SOI CMOS, this SP10T employs a series-shunt topology for the time-division duplex (TDD) transmitting (Tx) and receiving (Rx), and frequency-division duplex (FDD) transmitting/receiving (TRx) branches to handle the high GSM transmitter power. The measured P0.1 dB, insertion loss and Tx-Rx isolation in the lower/upper bands are 36.4/34.2 dBm, 0.48/0.81 dB and 43/40 dB, respectively, comparable to commercial products with no/little ESD protection in high-cost SOS and GaAs technologies. Feed-forward capacitor (FFC) and AC-floating bias techniques are used to further improve the linearity. An ESD-switch co-design technique is developed that enables simultaneous whole-chip design optimization for both ESD protection and SP10T circuits.

20.4 A 123-phase DC-DC converter-ring with fast-DVS for microprocessors

Inspired by The Square of Vatican City, a fully integrated step-down switched-capacitor DC-DC converter ring with 100+ phases is designed with a fast dynamic voltage scaling (DVS) feature for the microprocessor in portable or wearable devices. As shown in Fig. 20.4.1, this symmetrical ring-shaped converter surrounds its load in the square and supplies the on-chip power grid, such that a good quality power supply can be easily accessed at any point of the chip edges. There are 30 phases on the top edge and 31 phases on each of the other 3 edges, making 123 phases in total. The phase number and unit cell dimensions of this architecture can easily be adjusted to fit the floor plan of the load. The pads of the converter-ring are placed at the corners, and will not affect the pads of the load. Moreover, by using the proposed VDD-controlled oscillator (VDDCO), the frequency of which is controlled by varying its supply voltage, a hitherto unexplored feature of the multiphase DC-DC architecture is exposed: the control-loop unity gain frequency (UGF) could be designed to be higher than the switching frequency.

An NMOS-LDO Regulated Switched-Capacitor DC–DC Converter With Fast-Response Adaptive-Phase Digital Control

A fully integrated low-dropout-regulated step-down multiphase-switched-capacitor DC-DC converter (a.k.a. charge pump, CP) with a fast-response adaptive-phase (Fast-RAP) digital controller is designed using a 65-nm CMOS process. Different from conventional designs, a low-dropout regulator (LDO) with an NMOS power stage is used without the need for an additional stepup CP for driving. A clock tripler and a pulse divider are proposed to enable the Fast-RAP control. As the Fast-RAP digital controller is designed to be able to respond faster than the cascaded linear regulator, transient response will not be affected by the adaptive scheme. Thus, light-load efficiency is improved without sacrificing the response time. When the CP operates at 90 MHz with 80.3% CP efficiency, only small ripples would appear on the CP output with the 18-phase interleaving scheme, and be further attenuated at VOUT by the 50-mV dropout regulator with only 4.1% efficiency overhead and 6.5% area overhead. The output ripple is less than 2 mV for a load current of 20 mA.

A near-threshold, multi-node, wireless body area sensor network powered by RF energy harvesting

A wirelessly-powered, near-threshold, body area network SoC supporting synchronized multi-node TDMA operation is demonstrated in 65nm CMOS. A global clock source sent from a base-station wirelessly broadcasts at 434.16MHz to all sensor nodes, where each individual BAN sensor is phase-locked to the base-station clock using a super-harmonic injection-locked frequency divider. Each near-threshold SoC harvests energy from and phase locks to this broadcasted 434.16MHz waveform, eliminating the need for a battery. A Near-VT MICS-band OOK transmitter sends the synchronized local sensor data back to the base-station in its pre-defined TDMA slot. For an energy-harvested local VDD=0.56V, measurements demonstrate full functionality over 1.4m between the base-station and four worn sensors, including two that are NLOS. The sensitivity of the RF energy harvesting and the wireless clock synchronization are measured at -8dBm and -35dBm, respectively. ECG Lead-II/Lead-III waveforms are experimentally captured, demonstrating the end-to-end system application.

A 48-mW 18-Gb/s fully integrated CMOS optical receiver with photodetector and adaptive equalizer

A 65-nm CMOS monolithic optical receiver IC with on-chip photodetector (PD) using the p-well/deep-n-well (PW/DNW) junction is presented for short-range optical communication using 850-nm wavelength. An adaptive continuous-time linear equalizer (CTLE) with 33-dB tunable gain is employed to compensate for the limited PD responsivity and bandwidth. For 850-nm optical PRBS-15 inputs, the receiver achieves record data rates and efficiencies of 9 Gb/s at 5.35 pJ/bit and 18 Gb/s at 2.7 pJ/bit with the PD biased in 0.5-V standard mode and 12.3-V avalanche mode, respectively. The core chip occupies 0.23 mm2 and consumes 48 mW.

Wireless power link design using silicon-embedded inductors for brain-machine interface

This paper discusses the safety requirements, equivalent circuit model, and design strategy of wireless power transmission to neural implants. The most daunting challenge is the design of the integrated receiving coil on the implantable device whose size must be within the safety and regulation limits while providing sufficient power transfer and efficiency. A novel silicon substrate-embedded 3.6-μH spiral inductor has been designed to fit inside a 4.5 mm × 4.5 mm implantable IC as the receiving coil. Full-wave EM simulations show that in a practical brain-machine interface setting, wireless power in the range of 1-10 mW can be delivered at 5% efficiency to an implant at 1 cm below the head surface using signals between 2 to 5 MHz. To achieve a high transfer efficiency, the optimal impedance for loading the receiving coil is derived using the equivalent circuit parameters of a realistic 3D model of the entire wireless power link. The large parasitic capacitance of the “in-chip” inductor is methodically absorbed in the matching network to maximize the efficiency and power transfer.