C. Plossu

Characterization of Si–SiO2 interface states: Comparison between different charge pumping and capacitance techniques

The three‐level and spectroscopic charge pumping techniques, deep level transient spectroscopy and capacitance‐voltage measurements are both used to determine the energy distribution of Si–SiO2 interface states on submicrometer metal–oxide–semiconductor field‐effect transistors and metal–oxide–semiconductor capacitors. This study is a systematic comparative analysis between charge pumping techniques and capacitance measurements. The measurements have been performed on different structures (n‐ and p‐type materials, low and high interface states densities) and the performances of each technique have been compared.

Improvement of EEPROM cell reliability by optimization of signal programming

Abstract This paper presents an optimization study of electrically erasable programmable read-only memory (EEPROM) cell programming to increase the long-term reliability of the device. Based on a charge-sheet model of the memory cell, we suggest that our result show that it is possible to decrease the electric field across the tunnel oxide of approximately 0.8 MV/cm, when using a particular programming waveform with a double rise ramp. We get the same simulated injected charge in write mode (+15 fC) and in erase mode (−12 fC) with the optimized programming signal rather than with the standard one. Threshold voltage measurements confirm the simulation results. Moreover, the endurance test shows that this new programming signal improves the endurance of the memory cell without any change in the device technology, memory cell lifetime becomes four times longer.

LaAlO3/Si capacitors: Comparison of different molecular beam deposition conditions and their impact on electrical properties

A study of the structural and electrical properties of amorphous LaAlO3 (LAO)/Si thin films fabricated by molecular beam deposition (MBD) is presented. Two substrate preparation procedures have been explored namely a high temperature substrate preparation technique—leading to a step and terraces surface morphology—and a chemical HF-based surface cleaning. The LAO deposition conditions were improved by introducing atomic plasma-prepared oxygen instead of classical molecular O2 in the chamber. An Au/Ni stack was used as the top electrode for its electrical characteristics. The physico-chemical properties (surface topography, thickness homogeneity, LAO/Si interface quality) and electrical performance (capacitance and current versus voltage and TunA current topography) of the samples were systematically evaluated. Deposition conditions (substrate temperature of 550 °C, oxygen partial pressure settled at 10−6 Torr, and 550 W of power applied to the O2 plasma) and post-depositions treatments were investigated t...

Conduction properties of electrically erasable read only memory tunnel oxides under dynamic stress

Abstract The write and erase programmable operations in electrically erasable read only memories (EEPROM) which are based on Fowler–Nordheim tunneling injection through a thin tunnel oxide window have been reproduced on specific large area double polycrystalline (poly) test capacitors. These structures integrate the different stacked layers (upper control gate polysilicon layer; interpoly dielectric layer; floating gate polysilicon layer; tunnel oxide; N+ substrate) of the active area of a memory cell state transistor. Stress pulses similar to those used in the programming memory cells were applied to the upper polysilicon layer. The variations of the tunnel oxide electrical conduction properties after numerous write-erase cycles were studied by measuring the current as a function of voltage characteristics of the structure. The Fowler–Nordheim constants were obtained as a function of the number of stress cycles. A model based on a simple equivalent electrical circuit was then implemented to simulate the resulting variations of the floating polysilicon gate charge and of the threshold voltage of the structure in both write and erase modes. These variations were compared to those directly measured on a memory cell. It is shown that the closure of the programmable window in memory devices can be unambiguously attributed to a decrease of the tunnel oxide conductivity.

Extraction and evolution of Fowler-Nordheim tunneling parameters of thin gate oxides under EEPROM-like dynamic degradation

Abstract A new method is presented for the extraction of the Fowler-Nordheim (FN) tunneling parameters of thin gate oxides from experimental current-voltage characteristics of Metal-Oxide-Semiconductor (MOS) capacitors. In this technique, the classical low temperature FN current model is considered but an improved numerical procedure has been implemented for the calculation of the oxide electric field — gate voltage relationship. It is shown that this iterative method leads to an excellent fit of experimental data with theoretical curves for both p-type and n-type substrates, even in the case of high doping levels. The procedure allows the determination of both FN tunneling parameters and potential barrier heights at silicon and polysilicon interfaces with a systematic estimation of the statistical fitting errors on each parameter. It is applied here to the study of the variations of the FN tunneling parameters of thin oxides submitted to EEPROM-like dynamic degradation.

Quantitative study of charge trapping in SiO2 during bipolar Fowler-Nordheim injection

Abstract This work deals with the programming window closure observed in electrically erasable programmable read only memories as the number of write/erase cycles increases. This aging phenomenon is attributed to the build-up of oxide charge in the tunnel area. Capacitance–voltage and current–voltage measurements on 8.5 nm thick oxide MOS capacitors performed after constant current Fowler–Nordheim (FN) stresses showed interface states generation at both the anode and the cathode. A linear build-up of ‘slow’ states with the total injected charge was also observed at the cathode. Bulk oxide trapped charge and normalized centroid were deduced from the DiMaria technique. The bulk oxide charge build-up after FN stress is shown to follow a power law as a function of injected electron density over several decades. The charging kinetics have been explained by two components: trapping by native and generated traps. We have determined the different trap parameters (densities, capture cross-sections, generation rates and locations). By varying the stress current (polarity and density), we have noticed that the change in generated trap parameters is linear with the stress bias. We take finally a particular interest in the cumulating effects of different stresses. To our knowledge, such a complete study is absent from the literature and has to be done to predict the charge trapping kinetics due to non-constant stress which occur during memory write and erase operations.

Dynamic stressing of thin tunnel oxides : a way to emulate a single EEPROM cell programming function

Abstract An experimental set-up was implemented by which metal-oxide-semiconductor (MOS) capacitors are subjected to bipolar high voltage (up to 20 V) pulses similar to those used in programming electrically erasable programmable read-only memory (EEPROM) devices. Thin (9 nm) tunnel SiO2 oxides MOS capacitors were used. During stress, by means of capacitive coupling, the capacitors gate node was kept floating so its potential was equivalent to that of the isolated floating gate of a memory cell. The written and erased operations of memory cells which are based on Fowler–Nordheim (FN) tunneling injection mechanisms, were then reproduced on simple MOS capacitors. Via a high input impedance electronic circuit, the floating gate potential was monitoring. A model based on a simple equivalent electrical circuit was used to simulate the transient regime of the FN current and the resulting floating gate charge and potential during dynamic stressing. It was shown that the floating gate accumulated charge is proportional to the maximum control gate voltage but is independent of the control gate pulse rise time.

Effect of some technological parameters on Fowler–Nordheim injection through tunnel oxides for non-volatile memories

In this work the effects of various technological parameters on Fowler-Nordheim injection through thin (around 7.2 nm) silicon dioxide films in metal-oxide-semiconductor capacitors have been studied. Attention has been paid to the effect of gate geometry (round or strip gate) and area, substrate doping type (boron or phosphorus one), polycrystalline silicon gate structure (simple polysilicon or polysilicon-oxide-nitride-oxide-polysilicon structure) and tunnel oxide type (standard or nitrided silicon dioxide). The effect of all these parameters on Fowler-Nordheim tunneling injection and on the potential barrier height at both oxide injecting interfaces are usually neglected in literature and moreover the tunnel coefficients obtained from a simple capacitor are used in the simulation of programmable operations of electrically erasable programmable read only memories. Quasi-static capacitance (voltage) and current (voltage) measurements have been performed and the latter have been simulated by using a constant effective barrier height at the injecting interface. We have found that Fowler-Nordheim tunneling parameters and potential barrier height at both oxide injecting interfaces are affected by the substrate doping type, oxide type, gate geometry and gate structure but they are not affected by the gate area. Moreover in all structures, a difference between the barrier heights at the two injecting interfaces has been observed. The variation induced by the studied technological parameters on the potential barrier height are comparable to the variation induced by considering a constant (classical theory) or electrical field dependent (quantum theory) barrier height as reported in literature.

Use of the charge pumping technique to understand non-uniform n-channel MOSFET degradation

Abstract By using the charge pumping technique we have separated the interface state from the fixed charge effects when non-uniform MOSFET degradation is induced by hot-carrier injection under electrical stress. For n-channel MOSFETs we show that, after a hot-electron injection, hot-holes can also be injected into the gate oxide under the same stress conditions. In this article we also show, by the study of static characteristics before and after the electrical stress, that the transductance degradation ΔG m and the threshold voltage shift ΔV T (induced by a maximum substrate current stress condition) follow an Atn law, but with very different values of n .

Dynamic Fowler–Nordheim injection in EEPROM tunnel oxides at realistic time scales

Abstract The purpose of this work is to investigate the dynamic behaviour of Fowler–Nordeim injection through EEPROM tunnel oxides, in conditions representative of the standard device operation. An experimental procedure based on the acquisition of current transients induced by trapezoidal-shape short voltage pulses is presented. It is then used to evidence a rapid positive charging and to determine some of its properties. Implications regarding the device behaviour and modelling are finally discussed.